[SI-LIST] Re: Impact on Copper Thieving on 10G Routing
- From: "Khanna, Vikas" <Vikas.Khanna@xxxxxxx>
- To: "jeff.loyer@xxxxxxxxx" <jeff.loyer@xxxxxxxxx>, "sij99@xxxxxxxxx" <sij99@xxxxxxxxx>, "si-list@xxxxxxxxxxxxx" <si-list@xxxxxxxxxxxxx>
- Date: Fri, 7 Mar 2014 17:53:55 +0000
Sometimes PCB fabricator will do copper balancing on inner layers to prevent
PCB from warping.
Vikas
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On
Behalf Of Loyer, Jeff
Sent: Friday, March 07, 2014 10:29 AM
To: sij99@xxxxxxxxx; si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: Impact on Copper Thieving on 10G Routing
As far as I know, thieving is placed so far away from traces that its effects
are insignificant. The exception I've seen has been where they put thieving on
dual stripline layers, but that is an egregious error. If in doubt, you
should call out "thieving keepout" areas in your design.
Note: though thieving is primarily a plating aid (as I understand it), I have
seen many vendors put thieving on inner layers. I would appreciate anyone's
informed insight into why it's sometimes used on inner layers, and sometimes
not. I suspect it's to reduce the amount of useless etching, but haven't been
able to get a definitive explanation.
Jeff Loyer
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On
Behalf Of Jack Si
Sent: Thursday, March 06, 2014 11:54 PM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Impact on Copper Thieving on 10G Routing
Hi Experts,
What are the major impact created by Copper Thieving in the 10G signals and the
precautions to avoid it.
Thanks and Regards,
Jack
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