[SI-LIST] Re: Impact on Copper Thieving on 10G Routing
- From: "Mike Sharpes (msharpes)" <msharpes@xxxxxxxxxx>
- To: "jeff.loyer@xxxxxxxxx" <jeff.loyer@xxxxxxxxx>, "sij99@xxxxxxxxx" <sij99@xxxxxxxxx>, "si-list@xxxxxxxxxxxxx" <si-list@xxxxxxxxxxxxx>
- Date: Fri, 7 Mar 2014 16:10:08 +0000
Thieving on inner layers is generally used on multilayer laminations to even
out the thickness variations between 'signal' layers and 'plane' layers in the
stack-up to prevent resin voiding and delamination problems at copper
boundaries.
As an example, in high layer count laminations with a larger number of plane
layers, the plane keepout boundary from the board edge will be the boundary
between local thickness maximums and minimums. The resin flow in this area
during pressing and lamination can be tricky and can easily produce resin
voiding, blistering and delamination. This is a rejectable defect either
internal to the board shop's QC or if it meets other criteria is rejectable by
acceptability and performance specs by IPC (IPC-A-600 or IPC-6012) if you
happen to call those out. A good fix to this is simply to even out the
thickness variations between layers if/when possible.
Regarding thieving and keepouts. Our guidelines allow the board shop to add
thieving on any layer (you may have exceptions to this) in a non-interconnected
pattern at a minimum space of 1.75mm from any conductive feature. Depending on
the board type we may include several exceptions. For instance, 'do not shadow
traces in a dual stripline configuration'. Depending on your trace widths you
may need to increase thieving space from conductors on the shadow layer. Other
DfM gotcha's include excepting thieving in areas on primary and secondary side
void of solder mask (e.g. labeling areas, layer stack-up windows, slide wear,
mechanical attachment points, fiducial areas). And for those really paying
attention, having a thieving dot on an internal layer, like layer 2 in the
vicinity of a pick and place fiducial will 'really' drive your SMT manufacturer
nuts. So, except that area on inner layers somehow.
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On
Behalf Of Loyer, Jeff
Sent: Friday, March 07, 2014 8:29 AM
To: sij99@xxxxxxxxx; si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: Impact on Copper Thieving on 10G Routing
As far as I know, thieving is placed so far away from traces that its effects
are insignificant. The exception I've seen has been where they put thieving on
dual stripline layers, but that is an egregious error. If in doubt, you
should call out "thieving keepout" areas in your design.
Note: though thieving is primarily a plating aid (as I understand it), I have
seen many vendors put thieving on inner layers. I would appreciate anyone's
informed insight into why it's sometimes used on inner layers, and sometimes
not. I suspect it's to reduce the amount of useless etching, but haven't been
able to get a definitive explanation.
Jeff Loyer
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On
Behalf Of Jack Si
Sent: Thursday, March 06, 2014 11:54 PM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Impact on Copper Thieving on 10G Routing
Hi Experts,
What are the major impact created by Copper Thieving in the 10G signals and the
precautions to avoid it.
Thanks and Regards,
Jack
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