[SI-LIST] Re: I/O power integrity
- From: "Peterson, James F (EHCOE)" <james.f.peterson@xxxxxxxxxxxxx>
- To: "Jennifer Maharani" <jennifer.maharani@xxxxxxxxx>, <si-list@xxxxxxxxxxxxx>
- Date: Mon, 1 Dec 2008 08:57:24 -0500
Jenni,
I assume your question is related to modeling the IO loads for your IO
power study.
I wouldn't use an RC circuit. I would use a t-line load with an
appropriate termination at the end...that way your model is close to
reality. Trying to do this for all IO is hard, but you could do one for
each similar circuit (e.g. one for the 64 bit databus, then multiply x
64, then one for the 20 bit ADDR bus and x 20, etc.).
Regards,
Jim Peterson
Honeywell
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
On Behalf Of Jennifer Maharani
Sent: Wednesday, November 26, 2008 7:42 AM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] I/O power integrity
Dear all,
I am working on I/O power integrity. What kind of termination should I
use for the memory side? Can I use RC termination ?
Thanks,
Jenni
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