[SI-LIST] Re: I/O Planning for DDR3
- From: "Shao, Peng" <Peng_Shao@xxxxxxxxxx>
- To: "mervin.jacob@xxxxxxxxxxx" <mervin.jacob@xxxxxxxxxxx>, "si-list@xxxxxxxxxxxxx" <si-list@xxxxxxxxxxxxx>
- Date: Fri, 12 Oct 2012 05:37:00 +0000
Mervinï
You may try the IO Designer from MentorGraphics. This tool can tell you what is
the optimization for PCB layout, and can communicate the constrain file with
your FPGA design tool.
And you may ask for help/demonstration from local Mentor AE. Good luck!
Shaopeng
AE Consultant Mentor Graphics Electronic Technology Co., Ltd.
ÂTel:Â +86-10 - 5930 4050
Cell:Â +86-136 1105 7707
Fax:Â +86-10-6808 0319
E-mail: peng_shao@xxxxxxxxxx
Address: RM1512, CanWay Building, No.66 NanLiShi Lu, Beijing, China 100045
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On
Behalf Of Mervin J
Sent: 2012å10æ11æ 22:12
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] I/O Planning for DDR3
Hi,
I am working with the I/O planning of DDR3 interface in FPGA Design.
I was not able to get good reference for I/O planning in collaboration with
timing Analysis and also the parameters to considering during this planning to
have better tradeoff between the PCB designer and FPGA Designer.
Please suggest some idea or reference.
Thanks,
Mervin J
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