[SI-LIST] I/O Planning for DDR3
- From: Mervin J <mervin.jacob@xxxxxxxxxxx>
- To: "si-list@xxxxxxxxxxxxx" <si-list@xxxxxxxxxxxxx>
- Date: Thu, 11 Oct 2012 19:42:08 +0530
Hi,
I am working with the I/O planning of DDR3 interface in FPGA Design.
I was not able to get good reference for I/O planning in collaboration
with timing Analysis and also the parameters to considering during this
planning to have better tradeoff between the PCB designer and FPGA Designer.
Please suggest some idea or reference.
Thanks,
Mervin J
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