[SI-LIST] IEEE CPMT Society Phoenix Chapter - March 25 meeting
- From: Sampath K V K <sam_kvk@xxxxxxxxx>
- To: si-list@xxxxxxxxxxxxx
- Date: Thu, 27 Feb 2003 09:52:51 -0800 (PST)
This is a meeting announcement from the IEEE CPMT
Society Phoenix Chapter. All IEEE members and
non-members, in the Greater Phoenix area, are welcome
to attend.
INSTITUTE OF ELECTRICAL AND ELECTRONIC ENGINEERS
COMPONENTS, PACKAGES AND MANUFACTURING TECHNOLOGY
SOCIETY - PHOENIX CHAPTER MEETING
Date: March 25th, 2003, Tuesday
Location: Motorola, 2100 E.Elliot Road, Tempe AZ
(Group Conference Room)
Speaker: Mark Bohr, Intel Senior Fellow and Director
of Process Architecture & Integration,
Intel Corporation, Hillsboro, Oregon
Topic: Intel?s 90 nm Logic Technology
Agenda: 5:30-6:00 p.m. Social/Refreshments
6:00-7:00 p.m. Presentation
7:00 p.m. Dinner
ABSTRACT
The semiconductor industry continues down a path of
introducing new process technologies about every 2
years. Each new technology generation provides
roughly a 2x increase in transistor density and ~50%
increase in transistor performance. The key features
of Intel's next generation 90 nm logic technology will
be described, including the use of strained silicon
transistors with a 1.2 nm thick gate oxide, 7 layers
of copper interconnect with a new low-k dielectric,
and a 6-T SRAM memory cell with an area of 1.0 mm2.
Some of the issues encountered in packaging high
performance microprocessor chips will also be
discussed.
BIOGRAPHY
Mark Bohr received M.S. degree in electrical
engineering in 1978 from the University of Illinois,
Champaign-Urbana. He joined Intel?s Portland
Technology Development group in 1978 and has been
responsible for process integration and device design
on a variety of process technologies including recent
130 nm and 90 nm logic technologies used to make
Intel's high performance microprocessors. He is an
Intel Senior Fellow and Director of Process
Architecture & Integration and is currently directing
development activities for Intel's 65 nm logic
technology. He is the general chair for Intel Process
Technology Conference. He has published 29 technical
publications, offers two technical short courses at
IEDM, and holds 21 patents.
For more information, please call any of the following
officers of CPMT Society ? Phoenix Chapter:
Mali Mahalingam, Motorola (480) 413-5368
Sam Karikalan, Primarion (602) 659-4634
Rao Bonda, Motorola (480) 413-6121
Eric C. Palmer, Intel (480) 554-8710
Ravi Sharma, Microchip (480) 792-7920
Vasu Atluri, Intel (480) 554-0360
-----------------------------------------------
Regards,
Sam Karikalan
Vice Program Chair - IEEE CPMT Society Phoenix Chapter
Primarion, Inc.
2507 W Geneva Dr, Tempe AZ 85282
Tel.(602) 659 4634 Fax. (602) 454 7220
E-mail: sam.kvk@xxxxxxxxxxxxx
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