[SI-LIST] IEEE CPMT Society Phoenix Chapter - 9/22/03 meeting announcement

  • From: Sam Karikalan <sam_karikalan@xxxxxxxxx>
  • To: si-list@xxxxxxxxxxxxx
  • Date: Thu, 4 Sep 2003 09:50:04 -0700 (PDT)

IEEE CPMT Society Phoenix Chapter - meeting
announcement
-------------------------------------------------------
Date: Sep 22nd, 2003, Monday 
Speaker: Mr.Eric Tosaya, Procket Networks, Milpitas,
CA
Topic: Network VLSI Packaging

Location: Motorola, 2100 E. Elliot Road, Tempe AZ
(Group Conference Room) 

Agenda: 5:30-6:00 p.m. - Social/Refreshments;
6:00-7:00 p.m. - Presentation; 7:00 p.m. - Dinner 

IEEE Members & Non-members all are welcome to attend.

ABSTRACT

Historically ASICs have been used in multi-gigabit
systems found in today?s networks. The next generation
of networking systems requires a level of performance
that exceeds the capabilities of ASICs. COT VLSI are
needed to achieve the density and performance for the
next generation of networking equipment. These COT
VLSI devices drive a complex mix of package
performance requirements such as very high densities
of GHz speed signals, high power dissipation,
stringent signal & power integrity specs and many
years of 24/7 operational reliability. These demands
require high pincount customized packaging to meet the
next generation of network systems. 

This talk will focus on a core router system that uses
six VLSI devices created based on a COT flow. The
basic requirements of the router, which drove the VLSI
definition, will be reviewed, followed by a discussion
on how the needs of the VLSI led to the selection and
design methodology developed for the 58mm HiTCE CGA
packages. Included will be an overview of the
electrical and reliability data for this package
family. 

BIOGRAPHY

Mr. Eric Tosaya has been responsible for VLSI
packaging development for over three years at Procket
Networks, a core router company based in Milpitas, CA,
as the manager of its VLSI packaging development
group. Eric has held similar positions at Advanced
Micro Devices, NexGen, LSI Logic and Intel. Eric
started working on assembly and packaging at
Fairchild?s bipolar division after obtaining his
Masters degree in Ceramic Engineering from the
University of Washington.

---------------------------------------------------

Best Regards,
Sam Karikalan,
Asst. Program Chair - IEEE CPMT Society Phoenix
Chapter

Primarion, Inc.
2507 W Geneva Dr, Tempe AZ 85282
Tel. (602) 659 4634
E-mail: sam.kvk@xxxxxxxxxxxxx


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