[SI-LIST] IEEE CPMT SI Fundamentals Course in Irvine, CA on July 19th, 2013

  • From: Steve Pytel <steve.pytel@xxxxxxxxx>
  • To: si-list@xxxxxxxxxxxxx
  • Date: Tue, 4 Jun 2013 10:54:48 -0500

*Signal Integrity Fundamentals One Day Short Course*

*UC Irvine

*July 19, 2013

* *

* *

*Abstract*:           This one-day short course provides practicing design
engineers an in-depth introduction into the fundamentals of signal
integrity.  It covers the practical and theoretical aspects necessary to
design modern high-speed digital systems at the chip, package, and board
levels.  Attendees will learn from Stephen Hall and Howard Heck, two
leading experts from Intel Corporation.

*Instructors*:      *Stephen Hall and Howard Heck, Intel Corporation*


·   High Frequency SI Challenges

·   Transmission lines

·   Skin effect, dielectric loss, and surface roughness

·   Single-ended and differential signaling

·   Cross-talk

·   Eye diagram analysis

·   High-speed serial interconnections

·   Equalization and de-emphasis

·   Jitter

·   Simultaneous Switching Output noise (SSO)

·   Power distribution

 * *

* *

*Location*:          *Calit2 Building, UC Irvine*

*Date*:                  *Friday, July 19, 2013*

*                            8:00 am – 5:00 pm*

*Who Should*

*Attend*:              Engineers and engineering managers who need a
detailed introduction to signal integrity, layout engineers who support
high-speed design, and serial I/O buffer circuit designers.

*Register*:           http://www.eventbrite.com/event/5563921840

*Parking*:           There is a University fee of $7 for parking.  Parking
will be available in the Advanced Parking Structure (APS) off East Peltason

*Sponsors*:          IEEE CPMT Orange County Chapter, IEEE Orange County
Section, UC Irvine Professor Chin C. Lee, UC Irvine Professor Franco


*Instructors *

*Biographies*:    *Stephen Hall, Intel Corporation,* began his career in
1992 in the Special Purpose Processor Division of the Mayo Foundation
developing multi-gigabit modeling techniques for X-band digital radar and
serial optical links.  In 1996, Stephen accepted a job at Intel, where he
was lead designer for buses on Pentium® II, III and IV systems, coordinated
research with universities, led research teams in the area of high-speed
modeling and taught Signal Integrity courses.  In 2000, Stephen published
the textbook “High-Speed Digital System Design” through John Wiley & Sons
and is currently co-authoring a new book “Advanced Signal Integrity for
High-Speed Digital Designs” which will be published in the fall of 2008.  From
2003 to 2007, Stephen primarily researched new modeling and measurement
solutions for channel speeds as high as 30 Gigabits per second and is
currently leading PCIe3 channel development at Intel.

*Howard Heck, Intel Corporation* Since joining Intel in 1995, Howard has
held R&D engineering and management positions for system electrical
technologies (interconnect, power, EMI). He led the development team for
the Pentium® II 100 MHz Host Bus, earning an Intel Achievement Award, and
managed teams that defined and delivered technology solutions for Direct
RDRAM™, DDR II, Pentium® 4 Processor Host Bus, and Accelerated Graphics
Port (AGP) interfaces. Prior to joining DEG, he led the Advanced Signaling
Technologies team in Intel’s Systems Technology Lab, focusing on modeling,
simulation, measurement, and technology solution development for 10+ Gb/s
signaling. He currently leads the signal integrity effort for Larrabee and
Larrabee II.  Howard earned the B.S.Ch.E. degree from Northwestern
University in 1985, and the M.S.E.E. degree from the National Technological
University in 1994. From 1985-1995 he was employed by IBM’s printed circuit
board manufacturing and high performance packaging lab, where he led
electrical development of their HyperBGA™ packaging technology. Since 1997,
Howard has also held a position as an Adjunct Professor at the Oregon
Graduate Institute, where he teaches High Speed Digital Interconnect
Design. He has presented papers at several industry conferences, holds six
patents with four pending and is a Senior Member of the IEEE.

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