[SI-LIST] IBIS - timing for die to ball interconnect

From: "Peterson, James F (Chief Engineers)" <james.f.peterson@xxxxxxxxxxxxx>
To: "si-list@xxxxxxxxxxxxx" <si-list@xxxxxxxxxxxxx>
Date: Mon, 2 Jan 2012 18:38:08 +0000

Hey IBIS Wizards,

Now that our rise times are close to the interconnect prop time between the die 
and the package I/O pin, how does IBIS represent this interconnect delay?

Is the first order approximation of interconnect delay between die and IO pin 
suppose to be L_pin, R_pin, and C_pin?

Is the IBIS "Package Model" the more accurate answer? If so, is there more info 
on this? (also, I don't see this being used much in the IBIS models.)

Thanks.
Jim Peterson
Honeywell
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