[SI-LIST] Re: IBIS & the Simulator
- From: "Angulo, John" <john_angulo@xxxxxxxxxxx>
- To: "'twesterh@xxxxxxxxx'" <twesterh@xxxxxxxxx>,si-list@xxxxxxxxxxxxx
- Date: Tue, 28 Jan 2003 15:30:38 -0800
Point taken, Todd. Indeed, the IBIS V-T tables themselves usually do not
include the effect of the package parasitics. (These parasitics would be
documented under L_dut, R_dut and C_dut, and few models do so.) To precisely
validate the waveform from the SI tool against the V-T table under the
documented test fixture, you need to eliminate the package and simulate the
buffer in isolation. In Hyperlynx, this just means zeroing the RLC columns for
the pin in question under the [Pin] keyword.
By the way, C_comp presents a different subtlety - it IS included in V-T table
waveforms. So, if for some reason we wish to remove C_comp from a driving
buffer, we cannot just set C_comp to zero; we must also recalculate the V-T
tables to "de-embed" the capacitor. Fortunately, we generally don't need to
eliminate C_comp from a model. Of course we should always keep an eye on the
appropriateness of the C_comp value.
John Angulo
Hyperlynx Products
Mentor Graphics Corp.
john_angulo@xxxxxxxxxx
425-869-2320
-----Original Message-----
From: Todd Westerhoff [mailto:twesterh@xxxxxxxxx]
Sent: Tuesday, January 28, 2003 2:47 PM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: IBIS & the Simulator
John,
I have to disagree here. While I agree that a simulator should *nominally*
be able to simulate the buffer along with the package parasitics (i.e.
analyze the packaged part) - it's not clear to me that the IBIS standard has
any opinion about whether a simulator should be able to model a buffer on
its own.
We find the ability to model the buffer without the associated package
parasitics quite useful in certain circumstances. For instance, when
correlating an IBIS buffer against its Spice counterpart, we usually model
the buffer without the associated package load. The correlation (or lack or
it) becomes clearer and some of the associated problems become easier to
identify and resolve.
Todd.
Todd Westerhoff
High Speed Design Specialist
Cisco Systems
1414 Massachusetts Ave - Boxboro, MA - 01719
email:twesterh@xxxxxxxxx
ph: 978-936-2149
============================================
"When did the choices get so hard, with so much more at stake?
Life gets mighty precious when there's less of it to waste"
- Bonnie Raitt, "Nick of Time"
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx
[mailto:si-list-bounce@xxxxxxxxxxxxx]On Behalf Of Angulo, John
Sent: Tuesday, January 28, 2003 5:34 PM
To: 'siwave2000@xxxxxxxxx'; si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: IBIS & the Simulator
Dan,
Hyperlynx always simulates R_pkg, L_pkg, C_pkg and C_comp for all device
pins regardless of buffer direction. This is required by the IBIS standard,
and should be true of all SI tools.
Best regards,
John Angulo
Hyperlynx Products
Mentor Graphics Corp.
john_angulo@xxxxxxxxxx
425-869-2320
-----Original Message-----
From: SiWave [mailto:siwave2000@xxxxxxxxx]
Sent: Monday, January 27, 2003 1:37 PM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] IBIS & the Simulator
Does anybody know that the IBIS based simulator, Hyperlynx, for example,
will only take R_pkg, L_pkg, C_pkg and C_comp into consideration for
RECEIVER or will consider more?
Thanks
Dan
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