[SI-LIST] Re: IBIS, si simulators, modeling and other sources of correlation error
- From: "Jon Powell" <jonpowell@xxxxxxxxxxxx>
- To: <scott@xxxxxxxxxxxxx>, <cclewell@xxxxxxxxxxxxxx>
- Date: Tue, 1 Apr 2003 10:25:26 -0800
Just to add to what Scott said:
Just because you have a SPICE model, does not mean that it correlates in any
way (or in your area of interest) to reality. There are many SPICE models
out there
that have been "sanitized" to protect IP. These sanitized versions are
usually not as complete or accurate over the full range of operating
conditions as were the original physically correlated models they were
derived from. In fact, this issue was one of things considered when IBIS was
first being designed: protecting IP while giving the necessary data. (Not
saying success was achieved, but it was the plan). So even when you have a
SPICE model, you have to check to see how good it is.
jon
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx
[mailto:si-list-bounce@xxxxxxxxxxxxx]On Behalf Of Scott McMorrow
Sent: Tuesday, April 01, 2003 9:59 AM
To: cclewell@xxxxxxxxxxxxxx
Cc: jeff.loyer@xxxxxxxxx; twesterh@xxxxxxxxx; si-list@xxxxxxxxxxxxx;
rhaller@xxxxxxxxxx
Subject: [SI-LIST] IBIS, si simulators, modeling and other sources of
correlation error
Craig,
To clarify a bit. If one is comparing Spice simultations of
driver/receiver circuits to Ibis simulations of the same circuits,
usually the most glaring error will be in the creation of the IBIS
model. There are so many poor ones out there that the differences
between the IBIS simulator and Spice are huge. Once the IBIS model is
extracted correctly and correlated, then usually all sorts of other
errors begin to pop out. Some easily seen, some hidden in the details
of modeling. I can classify these in two areas. 1) differences in
simulation environments. 2) issues with modeling.
In area #1 board level signal integrity simulators are often poor at
correctly modeling the entire system. For example, component mounting
pads, their associated capacitance and inductance, are excluded from the
electromagnetic extraction. Only the traces themselves are extracted.
Another example in this category would be in the modeling and simulation
of lossy lines. In Spice we have many alternatives, since we can create
lossy line models in many different ways, each with it's own tradeoffs
and errors. In board level SI simulators, there is usually only one
way. Usually there is an embedded field solver which extracts the
parameters very quicky (in a matter of seconds) and then a simulator
which uses a standard lossy model for simulation. In general, this is
often some variant of the w-element algorithm. Given that the field
solution is taking only a few seconds per cross-section, there is no way
that fully coupled lossy parameters are being extracted completely,
which can give rise to significant errors. Usually frequency dependent
inductance is not extracted at all. Often a TEM approximation is used to
derive the inductance matrix from the capacitance matrix, which is
totally incorrect when we are dealing with lossy systems.
In some cases the algorithm being used is just plain wrong and gives
incorrect results for lossy lines. Unfortunately, board level signal
integrity tools rarely allow for other simulation or modeling methods to
be integrated into their environments. What they will do is to export
the circuit to external Spice simulators, or launch a Spice process.
Unfortunately, what is being sent into Spice is often still the result
of incorrect or incomplete modeling.
A final example of a major case #1 problem is in the area of ground and
power modeling. Most of these board level signal integrity tools do not
correctly model ground or power. Ground is often treated as a node 0
infinite current sink that is connected to all ground pins everywhere.
As you know, this invalidates coupled multi-line connector modeling, as
it does coupled multi-line package modeling. Additional modes of
propagation that result from including ground and power conductors into
the simulation model are ignored by most board level SI simulation
environments, causing minor simualation errors for low impedance ground
and power structures and high errors for higher impedance ground and
power structures.
In area #2, there are a number of generally areas of modeling that are
not well considered. Package models for semiconductor devices are
usually poor approximations of the actual substrate. The problems can
usually be categorized into the following areas.
* insufficient bandwidth for the extracted package sections.
* failure to correctly model the power and ground paths
* mixed models with loop inductances for power and ground, mutual
inductances for signals.
* losses not modeled
* resonance effects of package not accounted for
* silicon redistribution layers not modeled
* wirebonds modeled as single inductor, rather than coupled RLC circuit.
* package vias and feedthroughs not modeled.
* package plating tails not modeled.
* wrong topology used for package spice model.
Vias are rarely modeled and in most cases are not modeled well.
Via-to-via coupling within tight pitch fields like BGA breakout areas
are rarely modeled, yet have significant coupling effects in high
performance systems.
Connector modeling for edge card connectors always makes assumptions
(that are unstated) about the board which will plug into the connector,
and as such will differ from the actual circuit under many customer
design conditions. The largest area of assumption will be in the
placement of the plane under the finger card traces and pads. It is
almost universally assumed that this plane is a ground plane, when quite
often it is not. For well-grounded connectors, actual performance may be
significantly different than modeled performance, due to very large
power/ground return path loops and slots created when a designer uses
different power reference planes on opposite sides of the connector.
Incorrect assumptions and/or extraction methods are often used when
modeling lossy board traces. So what if the simulator can simulate the
lossy element if the modeling assumptions are not based upon reality
and/or verfied by measurement. And unfortunately, those measurements
are often poluted by poor measurement launch design, or interpretatation
of the results, due to unforseen or uncontrolled resonance conditions.
Connector model boundaries, assumptions and limitations are not well
delineated. Rarely have I ever seen a connector model that takes loss
effects into account. Loss simulations of backplanes will often be off
by 1/2 dB due to lack of loss modeling in the connectors Interactions
between the electromagnetics of the PCB and that of the connector are
often excluded in the modeling process, leading to questions in how to
complete the modeling of the underlying PCB structures such as pads and
vias, and questions about the accuracy at the connector/board transition
boundary.
Craig, these are just a few things that I can think of to elaborate on
my previous topics.
best regards,
scott
--
Scott McMorrow
Teraspeed Consulting Group LLC
2926 SE Yamhill St.
Portland, OR 97214
(503) 239-5536
http://www.teraspeed.com
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