[SI-LIST] IBIS model for CML differential buffers
- From: Mohammad Ali <mohammad.ali@xxxxxxxxxxx>
- To: si-list@xxxxxxxxxxxxx
- Date: Wed, 06 Nov 2002 06:22:22 -0600
Dear SI members,
Can anybody point me to some resource links (any article, paper or
presentations) where I can find some helpful information on how to
accurately generate IBIS models (pullup, pulldown, PC, GC etc.) for
CML (current mode logic) differential buffers? So far I have
succefully created models for TTL, CMOS and LVDS buffers operating
upto 622 Mb/s range. IBIS official websites and some EDA vendors
websites and discussion pages have some model development topics,
but none of them about CML technology.
Hazem Hegazy from Mentor Graphics and Arpad Muranyi from Intel
delivered excellent articles and presentations on LVDS modeling. I
am looking for something like those but on CML technologies.
Any helpful hints or links would be highly appreciated. Thanks.
-Mohammad Ali
--
================================================================
Mohammad W. Ali, Ph.D. Phone 630.378.8924
Tellabs Operations, Inc. Fax 630.378.8994
1000 Remington Blvd. Cell 630.430.1806
Bolingbrook, IL 60440 Email Mohammad.Ali@xxxxxxxxxxx
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