[SI-LIST] Re: IBIS model endpoints mismatch errors
- From: "Mike LaBonte" <milabont@xxxxxxxxx>
- To: <si-list@xxxxxxxxxxxxx>
- Date: Fri, 6 Aug 2004 12:27:24 -0400
Is the rising waveform actually settling? The number one reason for DC/AC
endpoints mismatch is that the simulation duration was not long enough for
the waveform to flatten out to the final steady-state value.
Mike LaBonte
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On
Behalf Of Anuj Chakrapani
Sent: Thursday, August 05, 2004 9:45 AM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] IBIS model endpoints mismatch errors
Hi:
I am generating an IBIS model from the Spice netlists
of I/O buffers available to me. I am using the s2ibis2
method for generation of the IBIS model.
The curves generated look fine. But, the IBISCHK3
parser flags the DC/AC endpoints mismatch error. From
the looks of it, it is obvious that the rising
waveform is settling to a value higher than the DC
endpoint. But, I am trying to figure out why.
Could this be because of the buffer design? Or is this
merely an accuracy issue of the tool used (i.e.,
s2ibis2)?
Your inputs would be much appreciated.
Thanks,
-Anuj.
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