[SI-LIST] Re: IBIS - Worst Case Corner package values

  • From: Hermann Ruckerbauer <hermann.ruckerbauer@xxxxxxxxxxxxx>
  • To: si-list@xxxxxxxxxxxxx
  • Date: Sun, 18 Mar 2012 14:41:24 +0100

Hello Mike,

thanks for the answer!

Just one Question:
You mentioned that you set the Package min and max values to the min and
max of all signals and use this for worst Case analysis.

Looking to this kind of IBIS files I mentioned here are not only Signal
Pins in the Pin Section but also e.g. Vref, Power, GND pins with huge
capacitance.
So your proposal is to manually change the original IBIS file and fill
the  max/min values out of the corresponding Signal Group that you are
simulating, right ?

I agree that this is a possible solution to do corner case simulation,
but i also do not really like to change files that I got from the device
manufacturer.

Is the IBIS Spec intending this manual change of IBIS files for corner
case simulation?
The simulator does need enough "intelligence" to generate fast/slow
corner cases. So does all simulators expect user modified IBIS files for
corner case simulations if this is not described in the Spec ? (at least
I have not found it...)

thanks and regards

Hermann

P.S. I got only one answer on this question, and  just a view out of
office notifications .. not sure if I did get all responses there ..



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schrieb Mike LaBonte:
> I like to set [Package] min and max values to the min and max of all signal
> pin values seen in the [Pin] section, and the typ to the mean  [Pin]
> values. A downside of this is that you often get a combination of max L and
> C values that don't occur on any actual pin, same for min. But [Package] is
> only useful for worst case analyses anyway. For modeling corners, or for a
> better package model in general, you need s-parameters. The IBIS keywords
> for that are being worked on.
> Mike
>
> On Sat, Mar 17, 2012 at 4:27 AM, Hermann Ruckerbauer <
> hermann.ruckerbauer@xxxxxxxxxxxxx> wrote:
>
>> Hello all,
>>
>> it would be great if somebody could help me with a question for IBIS
>> models (package related).
>>
>> In the past I got very often IBIS models that have been specific for any
>> special interface (e. g. the data bus of a memory Controller).
>> In the file there are RLC values for each pin individually ([PIN]
>> KeyWord). In addition there are the global package parasitics that cover
>> Min/typ/Max values of all the Signals included in the IBIS model
>> ([Package] KeyWord). Of course there is the additional [Package Model]
>> possible, but currently I'm talking about an IBIS file that does not
>> contain this feature. If only the Data bus interface is included the
>> [Package] min/max values allowed to do a corner case simulation with the
>> worst/best case values between all Signals of this interface. My
>> understanding was, that this was the intention of the  [Package]
>> definition.
>>
>> Over the years this changed and suppliers make IBIS files with all pins
>> and even different Components in one IBIS file. In this case the global
>> [Package] parameter does not make sense any more, because it is
>> containing values that are not related to the specific simulated
>> signals. E. g. there is one pin that is somehow connected to a plane one
>> get easily 30pF package parasitics. So for such packages the global RLC
>> min/typ/max values do not make any sense at all.
>> For Min and Max values the supplier could use NA in the IBIS, but
>> according to the spec 5.0 "Typically" must be specified. If this is the
>> mean value between PCIE, I2C, memory signals, planes ... this should not
>> be used in any simulation.
>>
>> If I'm running now a slow/fast corner case variation the simulator can
>> take either the [PIN] values, but these would not contain any
>> Manufacturing tolerances. If it is using the min/typ/max values from the
>> [Package] definition it might be completely off as it is using the
>> capacitance of a VDD plane.
>>
>> My questions would be:
>> - How should the models be done in case a complete device model with all
>> kinds of different interfaces is generated:
>>    - Leave [Package] min/max with NA? What do do with the typical value ?
>> - How should the Simulator handle Fast/Slow corner case simulation ?
>>    - I expect the package manufacturing tolerances are small, so just
>> take the given ("mean") RLC per pin ?
>>    - For any Package Corner Case simulation one need anyhow a better
>> package model
>> - Would it make sense to include some variation at the per pin package
>> RLC (e. g. a forth column stating +-5% variation) in the IBIS file ?
>> This would allow to     calculate a per pin Slow/Fast corner value
>>
>> Thanks for any feedback and insight how the IBIS model should be handled
>> in this topic.
>>
>> Best Regards
>>
>> Hermann
>>
>>
>> Our next Events:
>> ================
>>
>> Visit us on Embedded World 2012
>> Our location Hall 1 / Booth 509
>>
>> "Open the Black Box of Signal Integrity"
>> Seminar on 07. May 2012
>> "Open the Black Box of Memory"
>> Seminar on 09/10. October 2012
>>
>> Check our website or contact us for details
>>
>> EKH - EyeKnowHow
>> Hermann Ruckerbauer
>> www.EyeKnowHow.de
>> Hermann.Ruckerbauer@xxxxxxxxxxxxx
>> Veilchenstrasse 1
>> 94554 Moos
>> Tel.:   +49 (0)9938 / 902 083
>> Mobile: +49 (0)176 / 787 787 77
>> Fax:    +49 (0)3212 / 121 9008
>>
>>
>>
>>
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