[SI-LIST] Re: IBIS Model VT Curve Length
- From: "Muranyi, Arpad" <arpad.muranyi@xxxxxxxxx>
- To: <si-list@xxxxxxxxxxxxx>
- Date: Fri, 18 Apr 2003 10:59:43 -0700
I need to say a few words regarding this issue, since I do have
some experience with it.
Even though several tools can handle this situation without
generating discontinuities, this doesn't mean that the results
are going to be the same as what the transistor model gives.
And here I have to disagree with Jon's earlier posting in which
he said that there is enough information in the IBIS file to
handle this. I believe there is NOT enough information.
Consider the following situation. You are in the middle of a
falling edge when you start a rising edge. Conceptually the
tool can find the point at which it happens to be on the falling
edge waveforms of the model data, look it up on the rising edge
waveforms in the model data, and then just go back up using the
rising edge waveforms. This eliminates the discontinuity=20
that would happen if the rising edge would start at its beginning
at the time when the stimulus triggers it.
However, we need to look at a detail here. This algorithm basically
eliminates the beginning of the waveforms, which also include a
certain amount of internal buffer delay. (This is the horizontal
lead in portion of the waveform that is at the beginning of the
waveforms, which was also called the "dead zone" in this thread).
I ran a few comparisons between this algorithm and the SPICE model's
response, and found that an amount of delay equal to this "dead zone"
must be retained even in this situation (at least for the example I
tried). But because the algorithm jumps over it, the rising edge
will actually happen that much sooner than it supposed to.
This phenomena introduces an additional amount of skew between
edges that happen under this over clocked situation compared with
normal conditions. And this is why I also need to disagree with
another statement in this thread. This will effect simulations
doing source synchronous signals. The clock and data may not
both be over clocked, and if one jumps ahead and the other doesn't,
you will see the additional skew that is not there in reality.
I do have an algorithm suggestion, but the problem is that I do not
have proof for it working in general. I fear that there may be
cases when it may not give correct results, and this is also why
I believe that the IBIS data would have to include additional
information on how to handle this case.
Sincerely,
Arpad Muranyi
Intel Corporation
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-----Original Message-----
From: Scott McMorrow [mailto:scott@xxxxxxxxxxxxx]
Sent: Thursday, April 17, 2003 1:18 PM
To: mike_donnelly@xxxxxxxxxxx
Cc: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: IBIS Model VT Curve Length
Mike,
That's good to hear.
Anyone overclocking an IBIS model should, however, be aware that when=20
the device is run in this way, the output transistors are no longer=20
fully saturated. This will alter the average output drive strength and=20
capacitance, which will cause the measured delay and waveshape of the=20
driver to change. For relative timed busses, like source synchronous=20
busses, this would not be a major issue as long as all drivers are=20
identical. But for synchronously clocked systems, there can be some=20
additional timing skew between devices that are "overclocked" and=20
devices which are not.
YMMV
scott
--=20
Scott McMorrow
Teraspeed Consulting Group LLC
2926 SE Yamhill St.
Portland, OR 97214
(503) 239-5536
http://www.teraspeed.com
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