[SI-LIST] Re: IBIS Model Quality (or lack thereof)
- From: herbert_lage@xxxxxxxxxxx
- To: twester@xxxxxxxxxxx, si-list@xxxxxxxxxxxxx
- Date: Thu, 28 Mar 2002 15:25:32 +0100
Dear All,
My apologies for jumping into the discussion so late, but I was out of the
office for a couple of days and it took me a while to catch up with all the
contributions to this thread.
In response to Todd's original question, let me describe what Agilent
Technologies' components group does to verify our IBIS models which are
created for our fiber-optic transceivers and physical layer ICs. Most of the
critical high-speed I/Os work at GBit/s or higher datarates and are usually
implemented as (differential) PECL or CML buffers. For fiber-optic
transceivers we also make extensive use of EBD models. As we still consider
ourselves as newcomers to the field, we have done some work internally to
establish a process that hopefully helps us to develop models that provide a
reasonable description of the component's performance characteristics:
- Syntax is checked with the Hyperlynx Parser
- Buffer models are simulated in HSpice using the B-element and compared
with the original Spice simulations
- EBD models are translated into HSpice netlists
- Signals at output pins are simulated with a PRBS sequence and the
resulting eye diagrams are compared with measured eyes
We have published 2 white papers that give you more details about the
process.
The first paper is available from Agilent Technologies' website at
http://ftp.agilent.com/pub/semiconductor/morpheus/docs/intro_to_ibis.pdf
The second paper will be uploaded to our server on 1 May I believe, however,
if you contact me off the distribution list I can send it to you in advance.
I am not sure that we can guarantee that our models are always error-free,
however, we do have dedicated support in place to correct errors. If you
come across an error within any of our IBIS models, please do get in touch
with us via our IBIS webpage, or please contact your local field
applications engineer. Any other comments regarding our IBIS models are also
welcome as it does help us to improve model quality.
Best Regards,
Herbert Lage
Semiconductor Product Group
Agilent Technologies France
1, rue Galvani
91745 Massy Cedex
FRANCE
-----Original Message-----
From: Todd Westerhoff [mailto:twester@xxxxxxxxxxx]
Sent: Tuesday, March 26, 2002 11:55 PM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: IBIS Model Quality (or lack thereof)
Thanks everyone, for your contributions to this thread so far. By way of
summary, we've heard from the following semiconductor companies:
- Intel
- Fairchild
- Serverworks
(if I left anyone out, my apologies)
... and I'll vouch for both Intel and Micron myself, both in terms of model
quality and support.
It is my strong suspicion that precious few IBIS models are validated in any
meaningful way before they are shipped to the customer. A few of your have
expressed hopes for the IBIS model quality committee that has just gotten
started, I share your hopes and enthusiasm for the effort.
A number of you have outlined some of the testing processes you use, and I'd
like to suggest that we explore that subject a bit more. We've spent a LOT
of time here lately correlating IBIS models to their HSpice counterparts.
We're currently using two "standard" text fixtures to compare IBIS/HSpice
models:
* I/O buffer connected to VDDQ/2 through 50 ohms
* I/O buffer connected to 0.5ns, 50ohm tline, 5pf to GND at tline end
The theory is that the first test fixture compares rising/falling edge
characteristics and buffer strength, while the second test models the
driver's response to a reflected wave (primarily the value of C_Comp). If
you get the HSpice/IBIS buffers to agree across these two tests, chances are
the rest of the puzzle falls into place, provided you agree on things like
pin parasitics and switching thresholds.
So, I'm curious - for those of you who test IBIS models against any kind of
reference (HSpice or measurement) - what kinds of test loads are you using,
and what are you looking for?
As always, all input (on and off the list) is greatly appreciated.
Todd.
Todd Westerhoff
Signal Integrity Engineer
Hammerhead Networks
5 Federal Street - Billerica, MA - 01821
email:twester@xxxxxxxxxxx - ph: 978-671-5084
============================================
"I'm starting With the man in the mirror
I'm asking him to change his ways
And no message could have been any clearer
If you wanna make the world a better place
Take a look at yourself, and then make a change"
- "Man in the Mirror", Michael Jackson
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