[SI-LIST] Re: IBIS I/O model in HSPICE question

  • From: "Ingraham, Andrew" <Andrew.Ingraham@xxxxxx>
  • To: <si-list@xxxxxxxxxxxxx>
  • Date: Thu, 13 Feb 2003 10:28:39 -0500

I believe this is not a model issue.

As far as IBIS is concerned, how to stimulate a buffer is implementation
dependent.  IBIS doesn't really define HOW a simulator should make the
driver do its stuff.

HSPICE happens to implement IBIS models using a node voltage as a
"binary" control signal to tell the buffer when to switch.  Once it
starts to switch, its behavior should be independent of that control

I think this would be true regardless of whether you are using an IBIS
1.x model or an IBIS 2.x model.  Either way, HSPICE should tell the
model to "go do thy stuff, switch to the other state according to your
characteristics," and the control input should not affect it from that
point on.

The main exception to this, is if the control input is strongly
non-monotonic or toggles back before the IBIS buffer model has completed
switching.  Behavior is unpredictable if you try to switch an IBIS model
faster than it needs to get all the way from [Pullup] to [Pulldown] or
vice-versa; and people have observed bizarre output waveforms when
trying to do this (which are likely to be very simulator-dependent).

The HSPICE 2000.2 manual does say you can optionally use (for example) a
0-3.3V signal as the "digital" input; but it will be interpreted like a
0-1V signal that happens to go past 1.0V up to 3.3V.  That is, the IBIS
model starts switching at 0.8V on rising edges and 0.2V on falling
edges.  (I think the reason the thresholds aren't both 0.500V, is for
hysteresis in case of noise, mathematical or otherwise.)

I can think of a few things that might cause the behavior you describe.

How did you connect the 0-1V or 0-3.3V control voltage source?  Is it
between appropriate nodes ... do both nodes directly connect to the IBIS
B-element?  Be careful around package parasitics, which might introduce
an undesired feedback loop.  I think the B-element monitors the nd_in
node (V_in) relative to global GND.

Are you sure the input voltage waveform at the B-element node nd_in is
what you think it is?  Monitor it.  Is it precisely trapezoidal, or is
there any ringing, especially in the 0.2-0.8V range?  Try faster or
slower edges.  The edge rate at nd_in should have zero effect on the
output, except to shift the time when it starts switching (when the
input waveform crosses 0.2V or 0.8V).

Finally, we like to think that there's no interaction between nodes that
are electrically unconnected.  But SPICE is not perfect, and something
happening in one part of the circuit can sometimes mathematically affect
nodes elsewhere even if they aren't connected.  Remember, they are all
part of the same matrix operations within SPICE.  It is remotely
possible that the 0-3.3V waveform is doing this.  Keeping the timestep
lower, among other things, may help reduce this effect.


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