[SI-LIST] Re: IBIS ECL Clock issue.
- From: "John Ellis" <jellis@xxxxxxxxx>
- To: "'si list '" <si-list@xxxxxxxxxxxxx>
- Date: Tue, 2 Jul 2002 17:24:44 -0400
Hello Marlon,
Make sure the IBIS buffer is in the same directory as your spice deck.
Check the warning statements of the .lis file.
The model call is case sensitive, make sure you have the correct call.
If you are running in HSPICE version 2001.4, stop now and run it in an
earlier version such as 2000.4. There is a bug in the way 2001.4 handles
IBIS buffers, but usually it gives you output
John
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx
[mailto:si-list-bounce@xxxxxxxxxxxxx]On Behalf Of ramroopsingh, marlon
Sent: Tuesday, July 02, 2002 4:53 PM
To: 'si list '
Subject: [SI-LIST] IBIS ECL Clock issue.
Good day all,
I am trying to run a simulation in HSpice using the On semi,
mc100lve222_tq52_z.ibs model as the driver. However I am not getting any
output. The model was tested in ICX and it passes, so I am under the
assumption that the error is in my calling of the model.
The following test file shows how I am calling the IBIS model:
***** Test File to resolve IBIS issue******
.OPT POST
.OPTION PROBE
.PROBE TRAN v(110) v(111)
+ v(inp) v(inn)
.tran 0.01n 16n
*125MHz pulse
VINP inp 0 PWL(0 vm 200p vh 3.8n vh 4.2n vl 7.8n vl
+8.2n vh 11.8n vh 12.2n vl 15.8n vl 16n vm r)
VINN inn 0 PWL (0 vm 200p vl 3.8n vl 4.2n vh 7.8n vh
+8.2n vl 11.8n vl 12.2n vh 15.8n vh 16n vm r)
.PARAM VCC=3.3
.param vh=1
.param vl=0
.param vm='(vh+vl)/2'
b_output_ecl1 nd_pu 110 inp nd_pc nd_gc
+ file='mc100lve222_tq52_z.ibs' model='33V_OUT20'
b_output_ecl2 nd_pu1 111 inn nd_pc1 nd_gc1
+ file='mc100lve222_tq52_z.ibs' model='33V_OUT20 '
rterm1 110 0 50
rterm2 111 0 50
R100 100 0 0.1
.END
If anyone sees any errors or can make any suggestions with regards to their
experiences with this model, your feedback is greatly appreciated.
Thanking you in advance,
Marlon Ramroopsingh
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