[SI-LIST] Re: I2C SCL layout question
- From: Hirshtal Itzhak <ihirshtal@xxxxxxxxxx>
- To: "'Joseph.Rubinstein@xxxxxxx'" <Joseph.Rubinstein@xxxxxxx>, "prashant.jaiswar@xxxxxxxxx" <prashant.jaiswar@xxxxxxxxx>
- Date: Sun, 15 Dec 2013 06:48:53 +0000
Jon and Joe - Thank you very much!
You helped me a lot. Although I suspected this situation it helps to know this
is truly true... :)
Best Regards
Itzhak
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On
Behalf Of Rubinstein, Joseph
Sent: Wednesday, December 11, 2013 1:17 AM
To: jonathan.lloyd.riley@xxxxxxxxx; prashant.jaiswar@xxxxxxxxx
Cc: Hirshtal Itzhak; si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: I2C SCL layout question
"such that falling edge can now be faster than 1ns and so track length may
matter. But as the rising edge does most of the work, the fast falling edge
still may not make a big difference."
I don't necessarily agree with this statement. With I2C devices that now have
fast fall times, if you don't treat them as clocks you run the risk of getting
reflections causing a non-monotonicity at the falling edge. This could cause an
extra edge during the falling edge. I have seen issues on designs that did not
properly route the I2C since it was a "slow" signal. I often tell my peers
that the speed of the clock is not material, it is the edge rate.
Joe
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On
Behalf Of Jonathan Riley
Sent: Tuesday, December 10, 2013 2:48 PM
To: prashant.jaiswar@xxxxxxxxx
Cc: ihirshtal@xxxxxxxxxx; si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: I2C SCL layout question
I2C is extremely simple. When it was created by Philips 20+ years ago, the
expectation was that distances would be short relative to the edge rates.
The rise times are governed only by the pull-up resistors and stray capacitance
values, therefore always slow. The fall times were assumed to be slow as well,
hence no need to worry about SI effects and no need for clever protocols to put
things right.
These days things are not quite the same. Many people will use the I2C ports in
what are now much faster devices such that falling edge can now be faster than
1ns and so track length may matter. But as the rising edge does most of the
work, the fast falling edge still may not make a big difference. At least, not
to the I2C interface. It should be remembered that it can still couple
crosstalk into adjacent tracks so very sensitive analogue signals (and of
course low level RF) may be affected in this way.
The full specification is available for free download from Philips (now
NXP) so you can see for yourself all the matters that they considered at the
time to be important when using this bus.
Although not an SI issue, one little thing that you might find useful is to
remember that many I2C devices do not have a Reset pin. Those that do therefore
have the ability to break the protocol if say the CPU is reset during an I2C
operation. This is because this can leave the state machines in the peripherals
stuck in the middle of the operation, and there are no timeouts to recover the
situation. There are several possible ways to fix this, but none could really
be called "right" in the spirit of the bus specification. Using the pins as
GPIOs instead of I2C and manually forcing the generation of "stop" conditions,
or providing enough clocks to end an operation are commonly used.
Regards
Jon
On 10 December 2013 13:33, Prashant Jaiswar <prashant.jaiswar@xxxxxxxxx>wrote:
> There is no special consideration.
> However one needs to meet certain electrical characteristics mentioned
> in the spec.
> "The I2C bus electrical characteristics mandates the max. electrical
> load to be <400pF.
> Inclusive of interconnect trace capacitance and input capacitance of
> the loads connected to the bus".
> If you are operating the bus at high speed mode (3.4Mbit/s) ensure
> your layout meets the timing requirements.
> This holds true for other modes as well.
>
>
>
> On Tue, Dec 10, 2013 at 6:50 PM, Hirshtal Itzhak <ihirshtal@xxxxxxxxxx
> >wrote:
>
> > Hi all,
> > As far as I know the I2C bus doesn't need any special considerations
> > for SCL (clock) routing, such as T or other sophisticated topologies
> > for ensuring its signal integrity.
> > My questions are:
> >
> > (1) Is that true?
> > (2) If so, how is it possible? Does the I2C protocol include some
> > mechanism to overcome errors stemming out of a poor layout such as
> > daisy-chain?
> >
> > I hope someone knows something about this low-tech bus!
> >
> > Thanks
> > Itzhak Hirshtal
> > The information contained in this communication is proprietary to
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