[SI-LIST] Re: I need to compensate for component with too high an input capacitance.
- From: "Chris Cheng" <Chris.Cheng@xxxxxxxxxxxx>
- To: <art_porter@xxxxxxxxxxx>, <si-list@xxxxxxxxxxxxx>
- Date: Wed, 22 Mar 2006 13:20:04 -0800
Art,
I can understand that may be the case if it is 50% off. But 3X off ? I =
am leaning towards under estimating the ESD capacitance or may be even =
completely forgotten to include it.
-----Original Message-----
From: art_porter@xxxxxxxxxxx [mailto:art_porter@xxxxxxxxxxx]
Sent: Wednesday, March 22, 2006 1:04 PM
To: Chris Cheng; si-list@xxxxxxxxxxxxx
Subject: RE: [SI-LIST] Re: I need to compensate for component with too
high an input capacitance.
This disparity could well be due to the difference between free-space =
models and actual circuits. Free-space models are great if the connector =
or whatever is halfway between earth and the moon and there is nothing =
else in the vicinity. Unfortunately vendors can only create and validate =
free-space models because they have no clue what electromagnetic =
environment the designer will insert the connector into.=20
Art Porter
Agilent Technologies
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] =
On Behalf Of Chris Cheng
Sent: Wednesday, March 22, 2006 1:55 PM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: I need to compensate for component with too high =
an input capacitance.
This is an interesting problem. I have my share of excessive capacitance =
=3D
from many vendors.
My question is, why is it always excessive capacitance not under =3D
capacitance. I've never seen one that have too high an impedance at the =
=3D
pad. Or in another word, why does the I/O designer always under estimate =
=3D
his/her pad capacitance ? Is it mostly due to under estimating the esd =
=3D
structure ? Under estimate the bump capacitance ?=3D20
And I am not talking about 50% off, I am talking about 2-3x off like the =
=3D
problem listed below. Most vendor blames the package design but I found =
=3D
it hard to believe.
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx
[mailto:si-list-bounce@xxxxxxxxxxxxx]On Behalf Of brimdavis@xxxxxxx
Sent: Wednesday, March 22, 2006 7:45 AM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: I need to compensate for component with too high
an input capacitance.
( re-posting, apologies if any duplicates show up )
Tom wrote:
>
> They now claim that it is around 6 pF instead of 2 pF. This, they
> claim, is why driver with an 80 ps rising edge causes
> such "excessive ringing" on the input.
>
If the problem is ISI from the {re}reflections off the big
input C, one simple fix is to stick a differential pad in front
of the reflective load - see further notes below.
>
> How best to do this? I have done some spice analysis on a circuit
> that is known as the "constant resistance termination".
>
For another discrete-laden matching approach that can improve
rise time for a big C, google "T-coil peaking".
http://www.hagtech.com/pdf/tcoil.pdf
Chapter 10, The Art and Science of Analog Circuit Design,
Williams (ed.), 1995 ( chapter on T-coils )
I've done simple inductive matching for narrrowband clock inputs,
but have never been brave enough to try a fancier peaking scheme
for, say, a 64 bit wide differential bus.
>
> 3) Is there an all together differenct aproach that I have not
> thought of?
>
If you have net with plenty of signal margin, and/or a driver
with adjustable output strength, a simple way to get rid of the
ISI crud from the reflections is to put a differential attenuator
ahead of the reflective input.
As a differential attenuator preserves the line impedance,
it doesn't further degrade the rise time, and it can be placed
near, rather than exactly at, the end of the net.
This approach also has the side effect of making the external
signal probe-able by damping out the reflections if the probe point
is upstream of the pad.
You can get differential 100 ohm Zo attenuators in an 0404 size
package, with values of 0,1,2,3,4,5,6, and 10 db, stocked at DigiKey.
I recently posted some notes and simple simulations over on
comp.arch.fpga, illustrating this same sort of problem for a
fast non-back-terminated driver whacking an FPGA input with
really big C; the posts below have further explanation and
links to some pdf's and LTSpice files:
http://groups.google.com/group/comp.arch.fpga/msg/85db6dc0bca5c0da
http://groups.google.com/group/comp.arch.fpga/msg/ab999f47d42e50f8
http://groups.google.com/group/comp.arch.fpga/msg/95809af82ccbb550
Note, the huge VCC clamp DC offset seen in the Xilinx V4 IBIS files
from early March might have been fixed in their latest release.
Brian
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