[SI-LIST] Re: I need to compensate for component with too high an input capacitance.
- From: "Van den brande Koen" <kvandenb@xxxxxxxxxxxxxx>
- To: <si-list@xxxxxxxxxxxxx>
- Date: Mon, 20 Mar 2006 10:27:22 +0100
Tom,
For a 500Mbps application, we have reduced the rise/fall time by putting
a 6.8pF capacitor between the 2 traces of the differential TL at the
driver (CML). The cap must be placed as close as possible to the output
pins of the driver.
You can try to solder different capacitor values between the pins of
your driver to see if this works for you as well.
Regards,
Koen
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
On Behalf Of s.goedecke@xxxxxxxxxxxx
Sent: maandag 20 maart 2006 08:30
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: I need to compensate for component with too high
an input capacitance.
Hi Tom,
I don't know your design specifics. Sometimes people put AC coupling
caps in device application notes assuming the signal will go off the
board. But if the signal stays on the board, and the dc levels of the
signal driver and receiver are met, then the AC coupling cap can be left
out; the signals can be connected directly. I have no idea if this is
the case for your design, but I have seen similar extra caps in signal
paths, so I thought it worth mentioning.
good luck with your design,
Stephanie
si-list-bounce@xxxxxxxxxxxxx wrote on 03/19/2006 05:12:10 PM:
> Hi,
>=20
> I have designed a component into my system that does not behave as=20
> advertised. The input capacitance of the part, as I am told by the=20
> manufacturer, is far higher than was listed in the specification.
> They now claim that it is around 6 pF instead of 2 pF. This, they=20
> claim, is why driver with an 80 ps rising edge causes such "excessive=20
> ringing" on the input.
>=20
> There are no alternative parts on the market that are common mode=20
> compatible with all of the components in the signal chain. Because of=20
> the density of this system, in terms of layout, I need to use LVDS or=20
> CML parts with internal differential terminations (source and load).=20
> Also, I am running at 1.5 Gb/s, so the parts need to have both high=20
> bandwidth and low input capacitance.
>=20
> The only other part on the market that might do the job needs to have=20
> a 10 uF AC coupling cap in the signal path and I can not afford the=20
> space in the layout nor the extra AC coupling due to bandwidth issues=20
> (we also need to pass lower BW signals).
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> My best option, I feel, is to somehow soften the rising edge of the=20
> signal so as to reduce the ringing on the input to the troublesome=20
> component.
>=20
> How best to do this? I have done some spice analysis on a circuit that
> is known as the "constant resistance termination". I read about this=20
> at the Dr. Howard Johnson website. I even have the original book by=20
> Bode that describes it (although Bode did not use the same name for=20
> it). One leg of this termination is inductive and one leg is=20
> capacitive. The idea is that overall impedance of the termination=20
> remains constant during the rising/falling edge transition but the=20
> effect is to soften the edges. This works good in Spice. One resistor=20
> is placed in series with the input capacitance of the device and there
> is another leg, with an inductor and resistor, placed from the far end
> of the resistor to ground.
>=20
> However, this involves the use of three extra components for each leg=20
> of the differential pair. It would require 2 resistors and and=20
> inductor, calculated to be in the neighborhood of 7 pH. For a signal=20
> pair this is 6 new components at the receiving end.
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> Even if I eliminated one leg of the differential pair for short=20
> distances, layout space is still an issue (3 extra components). For=20
> the constant resistance termination I could use 402 size resistors but
> the Inductor is still a problem.
>=20
> 1) For the constant resistance termination, how do you all feel about=20
> using spiral wound Inductors in a PCB? I, personally, have no=20
> experience with them.
>=20
> 2) What other options are out there for an inductance? I thought of=20
> using a Ferrite chip but their reactance curves are not linear. I=20
> suppose that I could "tune" the design until I got to something=20
> close....
>=20
> 3) Is there an all together differenct aproach that I have not thought
> of?
>=20
> I would love some input from the group. I am sure that someone out=20
> there has faced similar difficulties.
>=20
> Tom
> tom_cip_11551@xxxxxxxxxxx
>=20
>=20
>=20
>=20
>=20
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