[SI-LIST] Re: Hyperlynx vs. Signal Explorer
- From: "Chris Cheng" <Chris.Cheng@xxxxxxxxxxxx>
- To: "si-list" <si-list@xxxxxxxxxxxxx>
- Date: Thu, 11 Jan 2007 15:45:47 -0800
>My talk come very expensive. Many dollars.
That's the problem, I don't care what you talk, I want to know what you =
do.=20
>A brief answer:...........Blah, blah, blah.......Got it?
No I don't, what has that got to do with post route simulation. What =
interation you are expected to do on your PCB if you have excessive core =
noise on your die. Redesign your package and wait 6 months for it to =
come back and do another "post route" analysis ? Does the PCB design =
even help beyond 200MHz core noise ?
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx
[mailto:si-list-bounce@xxxxxxxxxxxxx]On Behalf Of agathon
Sent: Thursday, January 11, 2007 11:02 AM
To: si-list
Subject: [SI-LIST] Re: Hyperlynx vs. Signal Explorer
Chris,
A very instructive reply from you. Of what, I'm not sure.
You are telling me you have no parrallism rules nor termination scheme =
nor
> topology constrain on these buses and have a free for all and use the =
post
> route analysis to tell yourself whether it work or not ? Your precious =
DDR2
> nibbles and strobes are not grouped routed switched turned in the same =
way
> and are randomly free running ?
>
No, you're saying that, "my precious". Free run. Good deal. Sounds =
good
to me.
Pwr integrity, that's another interesting subject. What exactly are you
> suppose to do in your post route analysis to verify those coupling and
> impedance profile issue you are talking about ?
>
I'm not a fan of "post-route sim"; it seems to be a marketing tool to =
sell,
uh, tools. I hope you're not using it. If you are, call me and I can
dissuade you. It won't help with PI, except to detect where return =
paths
on the board are forced inductive by layout and enough current induces =
noise
on a return plane. But then you need a 2.5-3D model or set. Correct; =
no
insight is gained into Z profile of pcb itself by signal sims.
"Pkg design", what exactly are you packaging designing with your post =
route
> PCB? Pick up every single net in your PCB memory bus and extract your
> package also and simulate the entire bus switching at the same time to
> verified it works ? I know many ways to do that without doing the =
above.
> BTW, are you doing the above or you are just talking about it. Talk is
> cheap, do you practice what you preach ?
>
Ah, it's "my kung-fu better than your king-fu, eh"? Vedy good. Yes, =
they
call me "Preacher".
I remember similar retorts from you in the past. Did you cut & paste =
them
here from old email, or did you actually read mine carefully? Sorry, =
if
you want the answer you can send me a proposal. My talk come very
expensive. Many dollars. On the other hand, I find it very cheap and =
easy
to fling challenges. Hey, look Ma, I'm gettin' good at this, too!
A brief answer: You need accurate signal switching current profile (I,
time) to establish current demand on die/pkg for Vio. Sims aren't
necessary; you can calculate it and use macromodel current sources, with
accurate time profiles per ball, and a voltage-supply model, to stim the
pkg/die and behold the vio noise. For Vcore, obtaining actual bare die
current profiles is the issue. Also, a good lumped or Sparam pkg model =
can
be converted to a Z profile in different tools, to correlate with =
estimates
(among those things that I can provide you after I receive your =
proposal).
If you violate the noise limits, then optimize & iterate. Got it?
What exactly are you supposed to do with coupling and impedance profile
> issue on the DIMM, do you even get a PCB model from your vendor ? Once
> again, talk is cheap, tell me what you are doing yourself, not what =
you
> heard from a conference or read from a paper.
>
This I say, no charge, just for you: Send me a proposal. I send you a
quote (not cheap, you know). Then I tell you all about Z profile of =
DIMM,
incl. how-to, dependence on # of rail loads and dimm connector and
optimization methods. Then you can tell me how all your knowledge, such =
as
it is, was immaculately conceived by you in a cave somewhere, with no
conferences or readings. No, I'm serious. I'd like to know. Until =
then,
"I'll never telllll". Others interested can ask offline & I'll answer
...for free.
"1+GHz serial links also need loss & ISI estimates for certain cases."
> Ok, if you have already constrain your length, via and parallelism =
rules
> pre-route, what is left to verify if the rules are met and there is no
> DRC ? Turn the table around, if you don't constrain the length,via and
> parallelism before hand, are you using your post-route simulation to =
assure
> it works ?
>
Yes, loss can be well estimated with calculation, without sims. But, =
ISI is
pattern & xtalk dependent. Hence, simulate. Can use PDA methods, too.
Sims are used to see how much you can push the envelope, since in =
certain
cases you have to. Hello?
Now, off you go and don't forget anything. :-)
On 1/10/07, Chris Cheng <Chris.Cheng@xxxxxxxxxxxx> wrote:
>
> No, I am serious. I want to know.
>
> You are telling me you have no parrallism rules nor termination scheme =
=3D
> nor topology constrain on these buses and have a free for all and use =
=3D
> the post route analysis to tell yourself whether it work or not ? Your =
=3D
> precious DDR2 nibbles and strobes are not grouped routed switched =
turned =3D
> in the same way and are randomly free running ?
>
> Pwr integrity, that's another interesting subject. What exactly are =
you =3D
> suppose to do in your post route analysis to verify those coupling and =
=3D
> impedance profile issue you are talking about ? "Pkg design", what =3D
> exactly are you packaging designing with your post route PCB ? Pick up =
=3D
> every single net in your PCB memory bus and extract your package also =
=3D
> and simulate the entire bus switching at the same time to verified it =
=3D
> works ? I know many ways to do that without doing the above. BTW, are =
=3D
> you doing the above or you are just talking about it. Talk is cheap, =
do =3D
> you practice what you preach ?
>
> What exactly are you supposed to do with coupling and impedance =
profile =3D
> issue on the DIMM, do you even get a PCB model from your vendor ? Once =
=3D
> again, talk is cheap, tell me what you are doing yourself, not what =
you =3D
> heard from a conference or read from a paper.
>
> "1+GHz serial links also need loss & ISI estimates for certain
> cases."=3D20
> Ok, if you have already constrain your length, via and parallelism =
rules =3D
> pre-route, what is left to verify if the rules are met and there is no =
=3D
> DRC ? Turn the table around, if you don't constrain the length,via and =
=3D
> parallelism before hand, are you using your post-route simulation to =
=3D
> assure it works ?
>
> -----Original Message-----
> From: si-list-bounce@xxxxxxxxxxxxx
> [mailto:si-list-bounce@xxxxxxxxxxxxx]On Behalf Of agathon
> Sent: Wednesday, January 10, 2007 5:54 PM
> To: si-list
> Subject: [SI-LIST] Re: Hyperlynx vs. Signal Explorer
>
>
> Chris,
> heh heh, yer funny...
>
> Good point. I think you know the answer:
> Basic timing & such is assumed ok. What's sim'd is crosstalk effect =
=3D
> where
> you're pushing things, termination placement, excessive vias (1st one =
is =3D
> the
> worst, though), proper termination scheme vs. topology (such as the =
=3D
> various
> ddr2 options... not necessarily a simple choice if not a dimm), pwr
> integrity (PI) for dimm stuff - esp. if there's pkg design. =3D
> Concerning
> the PI, there really are coupling and impedance profile issues at =3D
> ddr2-667
> on a dimm. 1+GHz serial links also need loss & ISI estimates for =3D
> certain
> cases.
>
>
------------------------------------------------------------------
To unsubscribe from si-list:
si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field
or to administer your membership from a web page, go to:
//www.freelists.org/webpage/si-list
For help:
si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field
List FAQ wiki page is located at:
http://si-list.org/wiki/wiki.pl?Si-List_FAQ
List technical documents are available at:
http://www.si-list.org
List archives are viewable at:
//www.freelists.org/archives/si-list
or at our remote archives:
http://groups.yahoo.com/group/si-list/messages
Old (prior to June 6, 2001) list archives are viewable at:
http://www.qsl.net/wb6tpu
Other related posts:
