[SI-LIST] Re: Hyperlynx vs. Signal Explorer
- From: "Peterson, James F \(EHCOE\)" <james.f.peterson@xxxxxxxxxxxxx>
- To: "si-list" <si-list@xxxxxxxxxxxxx>
- Date: Thu, 11 Jan 2007 14:00:13 -0600
Agathon -
You and Chris are both making some good points - and seem to speak from
experience.=20
but.......
If we only have 100s of pico-seconds of timing margin in our circuit, or
even less, how can we choose to not perform a post-route simulation? It
seems like we're gambling with our company's profits if we don't do
it...
take care,
Jim Peterson
Honeywell
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
On Behalf Of agathon
Sent: Thursday, January 11, 2007 2:02 PM
To: si-list
Subject: [SI-LIST] Re: Hyperlynx vs. Signal Explorer
Chris,
A very instructive reply from you. Of what, I'm not sure.
You are telling me you have no parrallism rules nor termination scheme
nor
> topology constrain on these buses and have a free for all and use the=20
> post route analysis to tell yourself whether it work or not ? Your=20
> precious DDR2 nibbles and strobes are not grouped routed switched=20
> turned in the same way and are randomly free running ?
>
No, you're saying that, "my precious". Free run. Good deal. Sounds
good to me.
Pwr integrity, that's another interesting subject. What exactly are you
> suppose to do in your post route analysis to verify those coupling and
> impedance profile issue you are talking about ?
>
I'm not a fan of "post-route sim"; it seems to be a marketing tool to
sell, uh, tools. I hope you're not using it. If you are, call me and I
can
dissuade you. It won't help with PI, except to detect where return
paths
on the board are forced inductive by layout and enough current induces
noise on a return plane. But then you need a 2.5-3D model or set.
Correct; no insight is gained into Z profile of pcb itself by signal
sims.
"Pkg design", what exactly are you packaging designing with your post
route
> PCB? Pick up every single net in your PCB memory bus and extract your
> package also and simulate the entire bus switching at the same time to
> verified it works ? I know many ways to do that without doing the
above.
> BTW, are you doing the above or you are just talking about it. Talk is
> cheap, do you practice what you preach ?
>
Ah, it's "my kung-fu better than your king-fu, eh"? Vedy good. Yes,
they call me "Preacher".
I remember similar retorts from you in the past. Did you cut & paste
them
here from old email, or did you actually read mine carefully? Sorry,
if
you want the answer you can send me a proposal. My talk come very
expensive. Many dollars. On the other hand, I find it very cheap and
easy to fling challenges. Hey, look Ma, I'm gettin' good at this, too!
A brief answer: You need accurate signal switching current profile (I,
time) to establish current demand on die/pkg for Vio. Sims aren't
necessary; you can calculate it and use macromodel current sources, with
accurate time profiles per ball, and a voltage-supply model, to stim the
pkg/die and behold the vio noise. For Vcore, obtaining actual bare die
current profiles is the issue. Also, a good lumped or Sparam pkg model
can be converted to a Z profile in different tools, to correlate with
estimates (among those things that I can provide you after I receive
your proposal).
If you violate the noise limits, then optimize & iterate. Got it?
What exactly are you supposed to do with coupling and impedance profile
> issue on the DIMM, do you even get a PCB model from your vendor ? Once
> again, talk is cheap, tell me what you are doing yourself, not what=20
> you heard from a conference or read from a paper.
>
This I say, no charge, just for you: Send me a proposal. I send you a
quote (not cheap, you know). Then I tell you all about Z profile of
DIMM, incl. how-to, dependence on # of rail loads and dimm connector and
optimization methods. Then you can tell me how all your knowledge, such
as it is, was immaculately conceived by you in a cave somewhere, with no
conferences or readings. No, I'm serious. I'd like to know. Until
then, "I'll never telllll". Others interested can ask offline & I'll
answer ...for free.
"1+GHz serial links also need loss & ISI estimates for certain cases."
> Ok, if you have already constrain your length, via and parallelism=20
> rules pre-route, what is left to verify if the rules are met and there
> is no DRC ? Turn the table around, if you don't constrain the=20
> length,via and parallelism before hand, are you using your post-route=20
> simulation to assure it works ?
>
Yes, loss can be well estimated with calculation, without sims. But,
ISI is pattern & xtalk dependent. Hence, simulate. Can use PDA
methods, too.
Sims are used to see how much you can push the envelope, since in
certain cases you have to. Hello?
Now, off you go and don't forget anything. :-)
On 1/10/07, Chris Cheng <Chris.Cheng@xxxxxxxxxxxx> wrote:
>
> No, I am serious. I want to know.
>
> You are telling me you have no parrallism rules nor termination scheme
> =3D nor topology constrain on these buses and have a free for all and=20
> use =3D the post route analysis to tell yourself whether it work or =
not=20
> ? Your =3D precious DDR2 nibbles and strobes are not grouped routed=20
> switched turned =3D in the same way and are randomly free running ?
>
> Pwr integrity, that's another interesting subject. What exactly are=20
> you =3D suppose to do in your post route analysis to verify those=20
> coupling and =3D impedance profile issue you are talking about ? "Pkg=20
> design", what =3D exactly are you packaging designing with your post=20
> route PCB ? Pick up =3D every single net in your PCB memory bus and=20
> extract your package also =3D and simulate the entire bus switching at =
> the same time to verified it =3D works ? I know many ways to do that=20
> without doing the above. BTW, are =3D you doing the above or you are=20
> just talking about it. Talk is cheap, do =3D you practice what you
preach ?
>
> What exactly are you supposed to do with coupling and impedance=20
> profile =3D issue on the DIMM, do you even get a PCB model from your=20
> vendor ? Once =3D again, talk is cheap, tell me what you are doing=20
> yourself, not what you =3D heard from a conference or read from a =
paper.
>
> "1+GHz serial links also need loss & ISI estimates for certain=20
> cases."=3D20 Ok, if you have already constrain your length, via and=20
> parallelism rules =3D pre-route, what is left to verify if the rules =
are
> met and there is no =3D DRC ? Turn the table around, if you don't=20
> constrain the length,via and =3D parallelism before hand, are you =
using=20
> your post-route simulation to =3D assure it works ?
>
> -----Original Message-----
> From: si-list-bounce@xxxxxxxxxxxxx
> [mailto:si-list-bounce@xxxxxxxxxxxxx]On Behalf Of agathon
> Sent: Wednesday, January 10, 2007 5:54 PM
> To: si-list
> Subject: [SI-LIST] Re: Hyperlynx vs. Signal Explorer
>
>
> Chris,
> heh heh, yer funny...
>
> Good point. I think you know the answer:
> Basic timing & such is assumed ok. What's sim'd is crosstalk effect =
=3D
> where you're pushing things, termination placement, excessive vias=20
> (1st one is =3D the worst, though), proper termination scheme vs.=20
> topology (such as the =3D various
> ddr2 options... not necessarily a simple choice if not a dimm), pwr
> integrity (PI) for dimm stuff - esp. if there's pkg design. =3D
> Concerning
> the PI, there really are coupling and impedance profile issues at =3D
> ddr2-667
> on a dimm. 1+GHz serial links also need loss & ISI estimates for =3D=20
> certain cases.
>
>
> On 1/10/07, Chris Cheng <Chris.Cheng@xxxxxxxxxxxx> wrote:
> >
> > Sorry for being simple minded.
> > In this day of source synchronous and serial buses.=3D3D20
> > What exactly is needed to simulate on your PCB once the match length
=3D
> and =3D3D
> > parallelism rules are constrained in your router and no DCR is
shown.
> >
> > -----Original Message-----
> > From: si-list-bounce@xxxxxxxxxxxxx
> > [mailto:si-list-bounce@xxxxxxxxxxxxx]On Behalf Of Beal, Weston
> > Sent: Wednesday, January 10, 2007 2:31 PM
> > To: si-list
> > Subject: [SI-LIST] Re: Hyperlynx vs. Signal Explorer
> >
> >
> >
> > This discussion comes up at least once a year and the answer is
still
> > the same. The best description I've seen was a couple of years ago.
=3D
> All
> > EDA tools suck if you use them long enough. The deeper you get into
=3D
> it,
> > the more bugs you find. Don't go too deep into it and you'll be
happy =3D
> in
> > your ignorance :)X=3D3D3D20
> >
> > Now, the useful answer is that you need to look at features beyond
> > functions. Every SI simulator simulates digital nets to some useful
> > accuracy. Does it interface well to your PCB layout tool? Do you
need =3D
> it
> > to? Does it output results in the way you want to use it? Does it
> > support models of the effects that you are concerned with? Does it =
=3D
> have
> > the post-processing (waveform measurement) that you need? Is the
cost
> > within your budget? Can you, and do you want to, automate the tool
for
> > your work flow?
> >
> > So before you go looking too far for the right tool, you should
figure
> > out what is the job you need to do. If you just want to simulate a
net
> > once in a while to show pretty waveforms to your manager then get
the
> > cheapest tool you can find that makes pretty waveforms and you both
=3D
> will
> > be happy for the immediate future. If you want a fully extensible,
> > highly accurate, feature rich SI tool then get ready to spend some
big
> > money and time to get it set up in your environment. Thereafter you
=3D
> will
> > find long-term joy. Most users want something in between. That's why
> > there are so many SI tools on the market. Decide what is important
to
> > you and then the choice of tool will be fairly obvious.
> >
> > Regards,
> > Weston
> >
> >
> > -----Original Message-----
> > From: si-list-bounce@xxxxxxxxxxxxx =3D
> [mailto:si-list-bounce@xxxxxxxxxxxxx]
> > On Behalf Of agathon
> > Sent: Wednesday, January 10, 2007 12:41 PM
> > To: si-list
> > Subject: [SI-LIST] Re: Hyperlynx vs Signal Explorer
> >
> > I recently received a comment about just this from an acquaintance:
> > ----
> > "Short answer: anyone trying to make full use of Cadence pcb si
tools
> > for
> > interconnect sim and who, nevertheless, recommends it could make
good
> > use of
> > counseling of some kind... or the receivers of that info could make
=3D
> good
> > use
> > of a polygraph test on the one recommending. All this based on 1st
> > hand
> > experience over time."
> >
> > ----
> > No info on Hyperlynx.
> >
> >
> >
> > On 1/9/07, cdomeny <craig.domeny@xxxxxxxx> wrote:
> > >
> > > We are considering adding a base-model (<GHz) SI tool to our PCB
> > design
> > > flow and have looked at Mentor Hyperlynx EXT and Cadence Orcad Sig
> > > Explorer. In research, it seems the Cadence tool does not actually
> > > perform "physical extraction", but is able to do a post-layout
> > analysis
> > > somehow. Can anyone help?
> > >
> > > Hyperlynx "seems" more mature, but cost ~2X. However, we are =3D
> concerned
> > > also about post-layout, and if Hyperlynx actually extracts the =3D
> layout,
> > > it seems like a more robust method.
> > >
> > > Any help, insight, or guidance is appreciated.
> > >
> > > Thanks, - Craig
> > >
> > > ------------------------------------------------------------------
> > >
> > >
> >
> >
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