[SI-LIST] How to simulate ESD test of one chip CMOS chip
- From: <ChrisCheng@xxxxxxxxxxxxxx>
- To: <si-list@xxxxxxxxxxxxx>
- Date: Mon, 6 Nov 2006 14:35:20 +0800
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Hi all,
=20
I have one problem. In the graph, IN+ is connected to the ground. How
can we get the energy distribution between the IN+ and IN- signal
trace when we input ESD signal into IN+. What simulation tool should I
use? Thanks.
=20
Best regards
Chris
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