[SI-LIST] Re: How to reduce the impedance?

  • From: "Istvan NOVAK" <istvan.novak@xxxxxxxxxxxxxxxx>
  • To: <Fu.Gerg@xxxxxxxxxxxx>, "Si-List (E-mail" <si-list@xxxxxxxxxxxxx>
  • Date: Fri, 12 Dec 2003 08:33:18 -0500

Greg,

One possibility to consider is to add ground traces next to
each of your signal traces on the top layer.  This will
create co-planar arrangement, and you can lower the
impedance.  In fact, if you do not need the bottom ground
for high current, and all the necessary routing can be done
on one layer, you can use a single-sided PCB.

Regards,

Istvan Novak
SUN Microsystems


----- Original Message -----
From: "Fu, Greg (傅廣操 IES)" <Fu.Gerg@xxxxxxxxxxxx>
To: "Si-List (E-mail" <si-list@xxxxxxxxxxxxx>
Sent: Thursday, December 11, 2003 10:53 PM
Subject: [SI-LIST] How to reduce the impedance?


> Hi all,
>      Recently we design a two layer board. It's designed as an =
> additional daughtercard to mothercard.
>      Its total height is 1.2mm.Top layer is signal, bottom layer is =
> Ground. Every layer is filled with 1OZ Cu. When we set the trace width =
> 10mil,then the trace impedance is so high(almost 120Ohm), it can't match =
> with mothercard's trace impedance(55Ohm).
>     Then keeping the daughtercard's total height, any way to lower the =
> impedance of daughtercard trace(if trace width is too big, no meaning in =
> practice). Any help will be greatly appreciated.
> Best regards,
> Greg
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