[SI-LIST] Re: How to properly simulate signal integrity across PCBs interconnected by Flex?
- From: Scott McMorrow <scott@xxxxxxxxxxxxx>
- To: CurtM@xxxxxxxxxxx
- Date: Fri, 31 Aug 2007 19:10:47 -0400
To add to this, Samtec has a line of connectorized Flex and Cable
interconnects that are designed specifically to handle high speed
signals. Any application information that you need is available either
on-line and through them. Also, for some of the assemblies, spice
models are available.
http://www.samtec.com/high_speed_connectors/2006/SI_C2B.asp?m=hs#HSF
By way of a disclaimer, we are associated with and do work for Samtec.
However, we have designed and characterized quite a few of these flexes
and cables.
Scott McMorrow
Teraspeed Consulting Group LLC
121 North River Drive
Narragansett, RI 02882
(401) 284-1827 Business
(401) 284-1840 Fax
http://www.teraspeed.com
Teraspeed® is the registered service mark of
Teraspeed Consulting Group LLC
Curt McNamara wrote:
> The answer to shipping clocks across flex:
> Don't do it if possible. Reconsider the system, perhaps distributed
> clocking would work, or even clock recovery from data. If you absolutely
> had to ship clock across flex, do it differentially on two layer flex.
> Next best would probably be two layer flex with ground plane under clock
> and really slow clock edges.
>
> Yes, it is likely to cause problems with emissions.
>
>
> Curt
>
> Some basics on flex:
> http://connectorwizard.com/reference/articles/pdfs/flex_webinar.pdf
>
> Curt McNamara, P.E. // senior electrical engineer=20
> Logic Product Development
> 411 Washington Ave. N. Suite 400
> Minneapolis, MN 55401
> T // 612.436.5178
> F // 612.672.9489
> www.logicpd.com=20
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> -----Original Message-----
> From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
> On Behalf Of jeanpierrepoulin
> Sent: Friday, August 31, 2007 3:04 PM
> To: si-list@xxxxxxxxxxxxx
> Subject: [SI-LIST] How to properly simulate signal integrity across PCBs
> interconnected by Flex?
>
>
> Hello Gurus,
>
> I am attempting to correctly design the first time a system=20
> consisting of five small PCBs interconnected by short (1-5 inch) Flex=20
> cable. While most signals are single ended and of moderate speed (20-
> 80 Mhz and with most edges controlled by the driving strength of FPGA=20
> drivers), I am particularly concerned about some clock signals that I=20
> need to spread to all these PCBs and wish to properly simulate...
>
> 1. Is there a flex connector vendor in particular that publishes=20
> quality IBIS model the simulating software will need?
>
> 2. What simulating software do you recommend as easiest to use for=20
> this type of need?
>
> 3. Do you think usage of Flex cabling in this fashion would cause =20
> problems during FCC certification?
>
> 4. Any good web site / publication you've seen on the subject of=20
> signal integrity across Flex cabling?
>
> Any hint you could offer is greatly appreciated!!
>
> Jean-Pierre Poulin
>
>
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