[SI-LIST] Re: How to measure the resistance, inductance and capacitance parasitic of a packaged chip?
- From: "Ihsan Erdin" <erdinih@xxxxxxxxx>
- To: jamesh235914@xxxxxxxxx
- Date: Mon, 27 Aug 2007 13:24:20 -0400
James,
The following paper exactly talks about what you're asking. Just like
TDR in the time domain, one can use the S11-parameter to extract the
equivalent circuit model of a discontinuity in the frequency domain.
Any optimization technique can be used but the genetic algorithm was
chosen for its non-gradient based algorithm that prevents it from
getting stuck to local minima in some cases.
Regards
Ihsan
Ihsan Erdin, "A Genetic Algorithm Based Interconnect Discontinuity
Model for Multi-Gb/s Circuits," The 2003 IEEE Int. Symposium on
Electromag. Compat. Istanbul May 2003
On 8/27/07, James H <jamesh235914@xxxxxxxxx> wrote:
> Dear All,
>
>
> I am studying how to measure the resistance, inductance and capacitance
> parasitic of a packaged chip. What is the best method to model and measure
> the parasitic of a chip+package? If I get S11 parametric by one port
> measurement, how could I use S11 parametric fit to get the resistance,
> inductance and capacitance value?
>
>
>
> Thanks & Best Regards,
>
> James H
>
>
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