[SI-LIST] How to measure the resistance, inductance and capacitance parasitic of a packaged chip?

  • From: "James H" <jamesh235914@xxxxxxxxx>
  • To: si-list@xxxxxxxxxxxxx
  • Date: Mon, 27 Aug 2007 23:38:01 +0800

Dear All,


I am studying how to measure the resistance, inductance and capacitance
parasitic of a packaged chip. What is the best method to model and measure
the parasitic of a chip+package? If I get S11 parametric by one port
measurement, how could I use S11 parametric fit to get the resistance,
inductance and capacitance value?



Thanks & Best Regards,

James H


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