## [SI-LIST] Re: How to measure the resistance, inductance and capac itance parasitic of a packaged chip?

• From: "Clewell, Craig" <Cclewell@xxxxxxxxxxxxx>
• To: "'jamesh235914@xxxxxxxxx'" <jamesh235914@xxxxxxxxx>
• Date: Mon, 27 Aug 2007 13:16:01 -0400

``` James,

For low frequencies I believe you could use a smith chart as long as your
DUT is less than a quarter wavelength at the frequency of interest.  Use a
short for the inductance and an open for the capacitance.  L would be equal
to the imaginary portion of the measurement from the smith chart divided by
2pi*f.  The capacitance is equal to 1 / (reflection coefficient*2pi*f).
These equations assume that the VNA reading is not normalized.  If the DUT
has significant losses, or the frequency gets too high the trace on the
smith chart will start to spiral inward because the impedance is no longer
purely imaginary making this method worthless.

You may be able to get more accurate measurements if you create two
identical structures that vary only in length.  This will help to reduce the
affects of the vias, probes, pads, etc if the paracitics of these things are
significant compared to the DUT.  If you use 2 structures you can take the
difference in the measured parasitics divided by the difference in the
length which will yield the L or C per unit length.

There may be other methods, but thought I  would just throw this out there
to chew on.

CC

-----Original Message-----
From: James H [mailto:jamesh235914@xxxxxxxxx]
Sent: Monday, August 27, 2007 11:38
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] How to measure the resistance, inductance and capacitance
parasitic of a packaged chip?

Dear All,

I am studying how to measure the resistance, inductance and capacitance
parasitic of a packaged chip. What is the best method to model and measure
the parasitic of a chip+package? If I get S11 parametric by one port
measurement, how could I use S11 parametric fit to get the resistance,
inductance and capacitance value?

Thanks & Best Regards,

H

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