[SI-LIST] Re: How good is enough(Power Integrity)
- From: bbolton <bbolton@xxxxxx>
- To: steve weir <weirsp@xxxxxxxxxx>, zhang_kun@xxxxxxxxxx
- Date: Fri, 23 Apr 2004 11:12:00 -0400
Zhangkun,
You're right in saying that capacitive decoupling requirments vary according
to the load. If you are dealing with a stand-alone SDRAM chip, for example,
the requirements would be different than an SDRAM memory stick. In general,
follow the manufacturer's guidelines to get the PDS right by design.
There are several ways to see if your PDS is well designed, and it depends on
the type of equipment available (consider short-term renting if necessary).
You can look at the voltage rail to determine if there is an under-voltage or
spike type condition present, which could be suppressed with additional &
correct capacitve values. Don't be fooled into adding lots of bulk (DC)
capacitance, when the device under test shows problems that really require
high-frequency bypassing. There is a point of diminishing returns for adding
caps of any value. Using a spectrum analyzer, under wost-case operating
conditions, (such as forcing all 0's and 1's on the bus as suggested) look for
peaks in the rail power spectrum to look for frequency regions that are
"asking" for more current but can't get it from the present PDS. Try to
"flip" the power spectrum and look for caps whose resonant frequency is
slightly higher than the peak you want to eliminate. You can iteratively add
caps to the problematic regions of the PCB and re-measure.
If this is your first PCB layout, pay close attention to capacitor placement,
as location matters. Even if you place the recommended capicatance on the
board, the layout folks may place the capacitor in the wrong place, or
inadvertently create large current loops or vias or 1/2" traces which nullify
your best efforts. Beware of autorouters. If you are still concerned about
the PDS design and EMI levels on a first-revision PCB, you may wish to add
unpopulated pads near anticpated trouble-components (< 0.1" ), and emperically
figure out which capacitor lowers the noise best, by varying capacitor values
and minimizing the measured the rail noise. The "best" PDS design may be a
combination of two good values -- such as a 6.8uF and 0.01uF pair that is
typically seen in high-frequency op-amp design. Of course, this becomes
incredibly expensive and is application dependent. Manufacturer's specs, and
iterative measurements tell you what you really need.
Of course if you start having problems, suspect I/O signal integrity, stackup,
current loops, parametric variations due to multiple-supplier ICs, or other
areas that might have been neglected in the design.
The best app-note that I have seen so far on PDS design is by Xilinx:
http://www.xilinx.com/bvdocs/appnotes/xapp623.pdf
Another good note by Altera is http://www.altera.com/literature/an/an315.pdf
Good luck!
Bryce
----------------------------------
Bryce Bolton
bryce.bolton@xxxxxxxxxxxxxxxxx
Desk: 303-735-5914
FAX: 303-735-4843
LASP (Laboratory for Atmospheric and Space Physics)
Attn: Bryce Bolton, Room 167
1234 Innovation Drive
Boulder, CO 80303
>===== Original Message From zhang_kun@xxxxxxxxxx =====
>Dear steve
>
>I do not express myself clear. What I want to say is that for different
chips, the request of decoupling are not same. For SDRAM, the impedance of PDS
could be large and for other chips, the impedance of PDS should be very small
to make the system work well.
>
>I want to know how to check whether the impedance of PDS is small enough or
not.
>
>Best Regards
>
>Zhangkun
>2004.4.23
>
>----- Original Message -----
>From: steve weir <weirsp@xxxxxxxxxx>
>Date: Friday, April 23, 2004 3:13 pm
>Subject: Re: [SI-LIST] How good is enough(Power Integrity)
>
>> Zhangkun, there are a whole lot of people who would take exception
>> to the
>> idea that SDRAM works well without decoupling. I suggest that if
>> you
>> perform a stress test that charges alternate columns in an entire
>> row to
>> all 1's, and then write all 0's to one half of the columns that
>> w/o
>> external decoupling capacitors you will see bit errors in the
>> unwritten
>> columns. A starting point for power integrity is to assign a
>> specific AC
>> noise voltage to the overall supply voltage tolerance budget, and
>> then
>> divide that by the AC current versus frequency to obtain an
>> impedance
>> versus frequency specification.
>>
>> Regards,
>>
>>
>> Steve.
>> At 02:00 PM 4/23/2004 +0800, zhangkun 29902 wrote:
>> >Dear All
>> >
>> >How good is enough in power integrity analysis at PCB level?
>> >
>> >In my experience, for some kind of general chip such as SDRAM,
>> even there
>> >is no decoupling caps for SDRAM, they will work well. However,
>> for some
>> >chips, the power ground noise is very critical.
>> >
>> >In signal integrity, there are plenty of model to simulate. In
>> power
>> >integrity, how to do?
>> >
>> >Any advice will be prefered.
>> >
>> >Best Regards
>> >
>> >Zhangkun
>> >2004.4.23
>> >
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