[SI-LIST] Re: How good is enough(Power Integrity)
- From: zhangkun 29902 <zhang_kun@xxxxxxxxxx>
- To: steve weir <weirsp@xxxxxxxxxx>
- Date: Fri, 23 Apr 2004 20:33:09 +0800
Dear steve
I do not express myself clear. What I want to say is that for different chips,
the request of decoupling are not same. For SDRAM, the impedance of PDS could
be large and for other chips, the impedance of PDS should be very small to make
the system work well.
I want to know how to check whether the impedance of PDS is small enough or not.
Best Regards
Zhangkun
2004.4.23
----- Original Message -----
From: steve weir <weirsp@xxxxxxxxxx>
Date: Friday, April 23, 2004 3:13 pm
Subject: Re: [SI-LIST] How good is enough(Power Integrity)
> Zhangkun, there are a whole lot of people who would take exception
> to the
> idea that SDRAM works well without decoupling. I suggest that if
> you
> perform a stress test that charges alternate columns in an entire
> row to
> all 1's, and then write all 0's to one half of the columns that
> w/o
> external decoupling capacitors you will see bit errors in the
> unwritten
> columns. A starting point for power integrity is to assign a
> specific AC
> noise voltage to the overall supply voltage tolerance budget, and
> then
> divide that by the AC current versus frequency to obtain an
> impedance
> versus frequency specification.
>
> Regards,
>
>
> Steve.
> At 02:00 PM 4/23/2004 +0800, zhangkun 29902 wrote:
> >Dear All
> >
> >How good is enough in power integrity analysis at PCB level?
> >
> >In my experience, for some kind of general chip such as SDRAM,
> even there
> >is no decoupling caps for SDRAM, they will work well. However,
> for some
> >chips, the power ground noise is very critical.
> >
> >In signal integrity, there are plenty of model to simulate. In
> power
> >integrity, how to do?
> >
> >Any advice will be prefered.
> >
> >Best Regards
> >
> >Zhangkun
> >2004.4.23
> >
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