[SI-LIST] Re: How do we choose the proper test load?
- From: "Jon Powell" <jonpowell@xxxxxxxxxxxx>
- To: <cycheng@xxxxxxxxxxxxxx>, <si-list@xxxxxxxxxxxxx>
- Date: Fri, 13 Jun 2003 07:11:45 -0700
If your goal is to use a static (or other) timing evaluator that uses models
based on the time delay of the parts in the databook, then it is important
that your SI measurement for test load be the same as the one used in the
databook for definition of time delay through the part.
What you are actually trying to do is remove the driving of the test load
from the equation to avoid double counting of that part of the delay.
jon
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]On
Behalf Of C.Y. Cheng
Sent: Friday, June 13, 2003 4:08 AM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] How do we choose the proper test load?
Dear list members,
I am confusing how to choose a proper test load for the timing evaluation.
In the book��High- speed digital system design�� page 204. There is an
example:
�� An output buffer with an edge speed of 300ps is driving a transmission
line with a C11 of 2.5pF/inch. And propagation delay of 150ps/in., the edge
would encompass 2 in. or 5pF. Subsequently, a good load in this case would
be 5pF.��
In this case, does the loading of receiver need to be considered to evaluate
the Tco if the trace length less than 2 inches?
This often asked by the logic designer. A capacitor often set at output pin
to extract timing for static timing analysis. The trace length in this case
may vary from 0.5 inch to 6 inches or more. How do we choose the test load
to cover all the case?
=================================
C.Y. Cheng
System Design Engineer
Realtek Semiconductor Corp.
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