[SI-LIST] How do we choose the proper test load?
- From: "C.Y. Cheng" <cycheng@xxxxxxxxxxxxxx>
- To: <si-list@xxxxxxxxxxxxx>
- Date: Fri, 13 Jun 2003 19:07:30 +0800
Dear list members,
I am confusing how to choose a proper test load for the timing evaluation.
In the book��High- speed digital system design�� page 204. There is an
example:
�� An output buffer with an edge speed of 300ps is driving a transmission
line with a C11 of 2.5pF/inch. And propagation delay of 150ps/in., the edge
would encompass 2 in. or 5pF. Subsequently, a good load in this case would
be 5pF.��
In this case, does the loading of receiver need to be considered to evaluate
the Tco if the trace length less than 2 inches?
This often asked by the logic designer. A capacitor often set at output pin
to extract timing for static timing analysis. The trace length in this case
may vary from 0.5 inch to 6 inches or more. How do we choose the test load
to cover all the case?
=================================
C.Y. Cheng
System Design Engineer
Realtek Semiconductor Corp.
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