[SI-LIST] Re: High/Low Frequency Jitter in PCIe Test

  • From: Joseph.Schachner@xxxxxxxxxx
  • To: Long Yang <long.0.yang@xxxxxxxxx>
  • Date: Tue, 21 Feb 2012 10:28:54 -0500

Re: "For PCIe 2.0, there are two jitter SPEC named high-freq jitter and 
low-freq jitter.
Can anyone explain what are the definitions of the two jitters?"
I think you are looking at Table 4-14, which is referred to in Note 1 of 
both Table 4-16 (Refclk Compliance parameters for Common Refclk 
architecture) and Table 4-18 (Refclock parameters for Data clocked Rx 
architecture).  Table 4-14 and the text above it explains the purpose 
without actually supplying test limits. The purpose is this: 
The low frequency range (0.01 - 1.5MHz) is assumed to be inside the 
tracking bandwidth of the Rx PLL.  There is a separate spec for the 
residual of SSC, so the ability of the Rx PLL to track SSC adequately is 
specifically checked.  The high frequency jitter (>1.5MHz) is assumed to 
be outside of the tracking bandwidth of the receiver's PLL, so this spec 
on the clock is how much jitter it can have in the frequency range where 
the Rx PLL may not follow it, so it could really appear to the receiver as 
jitter.

Below 10kHz is not checked because the assumption is that any Rx PLL can 
follow those frequencies "completely". What the spec actually says (in 
4.3.7.2.1.) is: "Lower edge of filter removes 1/f jitter contributions 
that are completely trackable by CDR. " (Personally, I think such an 
assumption is a test spec is suspect, but this one seems to have worked 
out).

Tables 4-16 and 4-18 give the actual limits for these jitter tests and 
notes explain the conditions under which the tests are made, for the 
stated architecture type. 

--- Joe S.



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