[SI-LIST] High speed signals go across isolation moat
- From: z46147 <zhuyongfa@xxxxxxxxxx>
- To: si-list@xxxxxxxxxxxxx
- Date: Wed, 14 Nov 2007 17:44:17 +0800
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Hi all,
A ten layers high speed PCB, the second layer is GND, the third layer is
signal, the fourth is Power layer.
GND plane is a full one, never been splited. Several types of voltage are on
the power layer, so the power layer is isolated by so many moats.
Thickness between the second and third layer is 7 mil, while 8 mil between the
third and fourth layer.
Some high speed signals traces are routed on the third layer, such as PCI
Express and SAS/SATA signals.
If the high speed signal traces go across isolation moat of the fourth power
layer, can it be treated as crossing split reference plane and give rise to
signal integrity problem?
If it will give rise to signal integrity problem, can we use stiching
capacitors across isolation moats of the power layer to deal with this issue,
while changing the
isolation moats?
Any thought on this issue would be appreciated.
Best regards.
Zhuyongfa
HUAWEI TECHNOLOGIES CO.,LTD.
Address: Huawei Industrial Base
Bantian Longgang
Shenzhen 518129, P.R.China
Tel:+86-755-89653025
Fax: +86-755-89650731
E-mail: zhuyongfa@xxxxxxxxxx
www.huawei.com
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