[SI-LIST] Re: High Speed Traces Under Card Edge Fingers
- From: steve weir <weirsi@xxxxxxxxxx>
- To: si-list@xxxxxxxxxxxxx
- Date: Sun, 08 Jan 2012 20:14:50 -0800
Simulation is never a bad idea. Assuming that because a given
connector's finger width is close to the trace width that the parasitics
are uniform through the transition and the connector is a bad idea.
Steve.
On 1/8/2012 7:58 PM, bala wrote:
> Whats your connector's SMT pad width&HS pair width.if they are almost
> equal,then no need to provide cutout.better get the models and simulate
> using HFSS or ADS.
> Thanks
> Bala
> On Jan 9, 2012 6:54 AM, "Stefan Milnor"<stefan.milnor@xxxxxxxxxxxxxx>
> wrote:
>> My PCB crew was routing some HS pairs along the edge under the fingers,
>> I was the bad cop and stopped them.
>>
>> If the planes are not pulled back, and the traces are isolated from the
>> fingers by planes, it would seem that the trace sig int would be OK.
>>
>> But I am getting the message that the "pullback is necessary" for the
>> connector sig int performance.
>>
>> Although - Devil's advocate - the only place I can recall seeing this in
>> print is in the PCIe CEM spec. I don't see this recommendation in the
>> MXM3 spec, or in the connector vendor's materials.
>>
>> Thanks, SM
>>
>> -----Original Message-----
>> From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
>> On Behalf Of steve weir
>> Sent: Sunday, January 08, 2012 5:46 AM
>> To: si-list@xxxxxxxxxxxxx
>> Subject: [SI-LIST] Re: High Speed Traces Under Card Edge Fingers
>>
>> The pullback is necessary to maintain a relatively constant impedance.
>>
>> Were you routing high speed signals on inner layers in the finger area?
>>
>> That's something I would avoid with or without the PCIe pullback
>> requirement.
>>
>> Steve.
>> On 1/7/2012 10:28 PM, Stefan Milnor wrote:
>>> Hello Experts
>>>
>>> The "DDR3 Clock Failing Radiation Tests" discussions have been quite
>>> interesting. But here is a different topic:
>>>
>>> "Remove Planes Under Card Edge Fingers?"
>>>
>>> In the PCIe CEM document, one finds the following statement:
>>>
>>> "On the add- in card, the ground and power planes underneath the PCI
>>> Express high-speed signals (edge fingers) shall be removed. Otherwise
>>> the edge fingers will have too much capacitance and greatly degrade
>>> connector performance"
>>>
>>> Is this really a concern?
>>>
>>> We are making small form factor boards with MXM3 connectors, and are
>>> wondering if we have to relieve the planes in the "edge finger" area.
>> If
>>> we do so, then we lose some routing space, for high speed signals at
>>> least, as we want to route these against a plain. This is a bit
>>> painful.
>>>
>>> Thanks,
>>>
>>> Stefan
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>>
>> --
>> Steve Weir
>> IPBLOX, LLC
>> 150 N. Center St. #211
>> Reno, NV 89501
>> www.ipblox.com
>>
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>
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--
Steve Weir
IPBLOX, LLC
150 N. Center St. #211
Reno, NV 89501
www.ipblox.com
(775) 299-4236 Business
(866) 675-4630 Toll-free
(707) 780-1951 Fax
All contents Copyright (c)2012 IPBLOX, LLC. All Rights Reserved.
This e-mail may contain confidential material.
If you are not the intended recipient, please destroy all records
and notify the sender.
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