[SI-LIST] Re: High Speed Traces Under Card Edge Fingers
- From: steve weir <weirsi@xxxxxxxxxx>
- To: si-list@xxxxxxxxxxxxx
- Date: Sun, 08 Jan 2012 23:11:36 -0800
Full-wave 3D tools certainly can.
Steve
On 1/8/2012 10:27 PM, Stefan Milnor wrote:
> Can current simulation tools and connector models really answer this
> question about GND plane "pull back" on edge cards? I am no simulation
> expert, but my understanding is that most simulation tools can not even
> handle plane splits.
>
> -----Original Message-----
> From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
> On Behalf Of Hermann Ruckerbauer
> Sent: Sunday, January 08, 2012 10:10 PM
> To: si-list@xxxxxxxxxxxxx
> Subject: [SI-LIST] Re: High Speed Traces Under Card Edge Fingers
>
> Hi,
> On Memory modules the Pullback is also done to adjust impedance of the
> wider fingers.
> I would assume that also on MXM3 the fingers are wider, so reduction of
> the impedance should make sense.
>
> As mentioned: Simulation can give a better answer then just assumptions
> ...
>
>
> Hermann
>
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>
> schrieb Stefan Milnor:
>> My PCB crew was routing some HS pairs along the edge under the
> fingers,
>> I was the bad cop and stopped them.
>>
>> If the planes are not pulled back, and the traces are isolated from
> the
>> fingers by planes, it would seem that the trace sig int would be OK.
>>
>> But I am getting the message that the "pullback is necessary" for the
>> connector sig int performance.
>>
>> Although - Devil's advocate - the only place I can recall seeing this
> in
>> print is in the PCIe CEM spec. I don't see this recommendation in the
>> MXM3 spec, or in the connector vendor's materials.
>>
>> Thanks, SM
>>
>> -----Original Message-----
>> From: si-list-bounce@xxxxxxxxxxxxx
> [mailto:si-list-bounce@xxxxxxxxxxxxx]
>> On Behalf Of steve weir
>> Sent: Sunday, January 08, 2012 5:46 AM
>> To: si-list@xxxxxxxxxxxxx
>> Subject: [SI-LIST] Re: High Speed Traces Under Card Edge Fingers
>>
>> The pullback is necessary to maintain a relatively constant impedance.
>>
>> Were you routing high speed signals on inner layers in the finger
> area?
>> That's something I would avoid with or without the PCIe pullback
>> requirement.
>>
>> Steve.
>> On 1/7/2012 10:28 PM, Stefan Milnor wrote:
>>> Hello Experts
>>>
>>> The "DDR3 Clock Failing Radiation Tests" discussions have been quite
>>> interesting. But here is a different topic:
>>>
>>> "Remove Planes Under Card Edge Fingers?"
>>>
>>> In the PCIe CEM document, one finds the following statement:
>>>
>>> "On the add- in card, the ground and power planes underneath the PCI
>>> Express high-speed signals (edge fingers) shall be removed.
> Otherwise
>>> the edge fingers will have too much capacitance and greatly degrade
>>> connector performance"
>>>
>>> Is this really a concern?
>>>
>>> We are making small form factor boards with MXM3 connectors, and are
>>> wondering if we have to relieve the planes in the "edge finger" area.
>> If
>>> we do so, then we lose some routing space, for high speed signals at
>>> least, as we want to route these against a plain. This is a bit
>>> painful.
>>>
>>> Thanks,
>>>
>>> Stefan
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