[SI-LIST] High Speed Traces Under Card Edge Fingers
- From: "Stefan Milnor" <stefan.milnor@xxxxxxxxxxxxxx>
- To: <si-list@xxxxxxxxxxxxx>
- Date: Sat, 7 Jan 2012 22:28:17 -0800
Hello Experts
The "DDR3 Clock Failing Radiation Tests" discussions have been quite
interesting. But here is a different topic:
"Remove Planes Under Card Edge Fingers?"
In the PCIe CEM document, one finds the following statement:
"On the add- in card, the ground and power planes underneath the PCI
Express high-speed signals (edge fingers) shall be removed. Otherwise
the edge fingers will have too much capacitance and greatly degrade
connector performance"
Is this really a concern?
We are making small form factor boards with MXM3 connectors, and are
wondering if we have to relieve the planes in the "edge finger" area. If
we do so, then we lose some routing space, for high speed signals at
least, as we want to route these against a plain. This is a bit
painful.
Thanks,
Stefan
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