Folks, We have quite a few openings in my group at San Jose and San Diego, CA. Experience in High speed Ser-Des applications, Signal Integrity, PC Board design, Verilog/VHDL design experience with high speed protocols like Fibre Channel, Gig Ethernet, XAUI, PCI Express is what we are looking for. A candidate with an EE/CS Engineering background with experience in one or more of the areas mentioned above would be suitable. A Physics/Mathematics background candidate with appropriate experience will also be considered. There is flexibility in the number of years of experience. Appropriate New College Graduates will be considered. A link to the job descriptions is provided below: http://www.altera.com/corporate/jobs/reqs/0438.html http://www.altera.com/corporate/jobs/reqs/0583.html http://www.altera.com/corporate/jobs/reqs/0359.html Regards, Vipul. -------------------------------------------- Vipul Badoni Sr. Manager, High Speed IO Applications Engineering Altera Corp. M/S: 2102 101 Innovation Dr. San Jose, CA 95134 Tel: (408) 544-8312 Fax: (408) 544-6466 e-mail: vbadoni@xxxxxxxxxx ------------------------------------------------------------------ To unsubscribe from si-list: si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field or to administer your membership from a web page, go to: //www.freelists.org/webpage/si-list For help: si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field List FAQ wiki page is located at: http://si-list.org/wiki/wiki.pl?Si-List_FAQ List technical documents are available at: http://www.si-list.org List archives are viewable at: //www.freelists.org/archives/si-list or at our remote archives: http://groups.yahoo.com/group/si-list/messages Old (prior to June 6, 2001) list archives are viewable at: http://www.qsl.net/wb6tpu