[SI-LIST] Re: Help me on power integrity simulation

  • From: steve weir <weirsi@xxxxxxxxxx>
  • To: si-list@xxxxxxxxxxxxx
  • Date: Wed, 11 Dec 2013 02:19:03 -0800

BTW, the SI-LIST discards attachments. No one will see your plots.

Steve.
On 12/11/2013 1:11 AM, sureshkumar.ayyavu@xxxxxxxxx wrote:
> Hi Dudes,
>
> Currently I'm doing PCB power integrity simulations on Sigrity Power SI.
> I've done the initial simulation by assigning decoupling capacitor S
> parameter models and ports to the power net that I need to simulate.
>
> After the result , i got some resonant peaks in the low frequency and high
> frequency regions. For instance , I got the peaks at 5Mhz & 40 Mhz. Then I
> tried to suppress these peaks by substituting the decaps which has low ESR
> value at the resonant peak frequencies. For the decoupling capacitor
> placement , I 've the placed low value caps near the DUT so as to suppress
> the hign frequency peak and placed the higher value cap near the source , in
> my case banana jack in order to suppress the low frequency peak.
>
>   
>
> But after the simulation , I don't see much difference between the impedance
> plots (attached). My target frequency is 0.1 ohm.
>
>   
>
> Guys , please help me to clarify this. How to optimize the plot ?
>
>   
>
> To select the cap for optimization , I go for TDK capacitor search page.
>
>
>
> Thanks
> suresh
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