[SI-LIST] Help me on power integrity simulation
- From: "sureshkumar.ayyavu@xxxxxxxxx" <sureshkumar.ayyavu@xxxxxxxxx>
- To: "si-list@xxxxxxxxxxxxx" <si-list@xxxxxxxxxxxxx>
- Date: Wed, 11 Dec 2013 09:11:56 +0000
Hi Dudes,
Currently I'm doing PCB power integrity simulations on Sigrity Power SI.
I've done the initial simulation by assigning decoupling capacitor S
parameter models and ports to the power net that I need to simulate.
After the result , i got some resonant peaks in the low frequency and high
frequency regions. For instance , I got the peaks at 5Mhz & 40 Mhz. Then I
tried to suppress these peaks by substituting the decaps which has low ESR
value at the resonant peak frequencies. For the decoupling capacitor
placement , I 've the placed low value caps near the DUT so as to suppress
the hign frequency peak and placed the higher value cap near the source , in
my case banana jack in order to suppress the low frequency peak.
But after the simulation , I don't see much difference between the impedance
plots (attached). My target frequency is 0.1 ohm.
Guys , please help me to clarify this. How to optimize the plot ?
To select the cap for optimization , I go for TDK capacitor search page.
Thanks
suresh
------------------------------------------------------------------
To unsubscribe from si-list:
si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field
or to administer your membership from a web page, go to:
//www.freelists.org/webpage/si-list
For help:
si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field
List forum is accessible at:
http://tech.groups.yahoo.com/group/si-list
List archives are viewable at:
//www.freelists.org/archives/si-list
Old (prior to June 6, 2001) list archives are viewable at:
http://www.qsl.net/wb6tpu
Other related posts:
