[SI-LIST] Re: Help! SDA suffered crosstalk from SCL, Fall time increased!

  • From: Tayyab Rahimkhan Pathan <Tayyab_Pathan@xxxxxxxxxxx>
  • To: "imerxu@xxxxxxxxx" <imerxu@xxxxxxxxx>
  • Date: Thu, 13 Sep 2012 14:02:13 +0000

Are you using any noise bypass cap on SDA/SCL like 33pF or so?
Can you elaborate the I2C bus design with CLK Freq, number of slave devices and 
bus length details?

Regards,
Tayyab

-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On 
Behalf Of Rohit MISHRA
Sent: Thursday, September 13, 2012 6:24 PM
To: imerxu@xxxxxxxxx
Cc: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: Help! SDA suffered crosstalk from SCL, Fall time 
increased!

Hello Alvis,

There is no waveforms attached with your mail as attachment is prohibited in 
si-list.

You rightly pointed out that rise/fall time depends on capacitance of line but 
question is what is the total capacitance SDA line will see ? 

Actually capacitance seen by SDA line is the sum of capacitance between SDA 
line and ground(C1) & capacitance between SDA and SCL line(C2) and I hope you 
know that when you talk about crosstalk between SDA & SCL, it's the C2 that is 
the culprit for the crosstalk ( Here I assume inductive crosstalk is negligible 
!)

Now when SDA and SCL lines are at same potential, SDA line will see less 
capacitance (C1) (As both plates of C2 have same potential so can't be charged 
!) that means fast rise/fall time but when SDA and SCL are at different 
potential, SDA line will have to charge both C1 and C2 that means more 
capacitance and hence more rise/fall time.

Hope that helps.

Rgds,
Rohit Mishra




-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On 
Behalf Of Imer Xu
Sent: Thursday, September 13, 2012 5:20 PM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Help! SDA suffered crosstalk from SCL, Fall time increased!

Hi all,
Here's the situation I'm facing: SDA and SCL of the same I2C device are 
crosstalking with each other. But what I'm confused is that if crosstalk 
happens near the fall edge of SDA, the falling will be slower, hence the fall 
time will increase(from 8ns of normal to 88ns)!  From my point of view, every 
time SDA falls to "0", no matter when falling edge of SCL happens, we are 
discharging the same capacitor(parasitic) via the same resistor (in other way, 
we are driving the same MOSFET of the open drain circuit of the I2C bus), the 
slew rate or fall time of the SDA falling edge should be the same. Please help 
with this problem: how could crosstalk affect fall time?
You could refer to the attached waveforms I captured.
I'm a newbie for SI, many thanks to your attention and help :)

Best Regards
Alvis Xu



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