[SI-LIST] Re: HSTL standard question,
- From: "Henrik G. Madsen" <hgm@xxxxxxxxxxx>
- To: <romeo@xxxxxxxxxxx>, <si-list@xxxxxxxxxxxxx>
- Date: Fri, 23 May 2003 08:51:30 +0200
Romeo,
The JEDEC HSTL standard (EIA/JESD8-6) do not state a strict requirement =
of a Vddq, its optional. Read the first paragragh in the standard, i.e. =
1 Scope.
The way I interpret the standard is that the strict requirement is:
Voh(DC)max <=3D 1.6 V (VDDQmax)
Voh(DC)min >=3D 1.0 V (VDDQmin-0.4V).
This can be obtained with or without a VDDQ
Regards
/Henrik G Madsen
-----Original Message-----
From: Romeo Iacobut [mailto:romeo@xxxxxxxxxxx]
Sent: 22. maj 2003 17:36
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] HSTL standard question,
Hello,
Sorry for the slightly off-topic post, but I have not any place to
ask this.
In JEDEC standard for HSTL , there are speciefied the supply voltage
levels: Vdd(Device supply voltage), Vddq(output supply voltage), and
Vref(input reference voltage).
My concerns are regarding to Vdd and Vddq.=20
If I have a 3.3V CMOS technology, how I will deal with Vddq(which is
fixed at 1.5V)? Output supply voltages is reffering at the last stage
of the buffer? For that I need a different supply (1.5V)?=20
Thank you in advance for any inputs/suggestions and patience.
Regards,
ROmeo
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