[SI-LIST] HSTL single ended bus to FPGA EVB Connector

  • From: משה פריד <moshef108@xxxxxxxxx>
  • To: si-list@xxxxxxxxxxxxx
  • Date: Tue, 14 Apr 2015 14:03:03 +0300

Can someone suggest on how to connect HSTL unidirectional signals to HPC
connector of FPGA EVB
The problem is that the HSTL is 1.8V max

The I/O on the HPC connector are only on 2.5V Bank.



Thanks



Moshe


------------------------------------------------------------------
To unsubscribe from si-list:
si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field

or to administer your membership from a web page, go to:
//www.freelists.org/webpage/si-list

For help:
si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field


List forum is accessible at:
http://tech.groups.yahoo.com/group/si-list

List archives are viewable at:
//www.freelists.org/archives/si-list

Old (prior to June 6, 2001) list archives are viewable at:
http://www.qsl.net/wb6tpu


Other related posts:

  • » [SI-LIST] HSTL single ended bus to FPGA EVB Connector - משה פריד