[SI-LIST] HSTL (QDR) Terminations
- From: "Aaron Frank" <aaron@xxxxxxxxxxxxx>
- To: <si-list@xxxxxxxxxxxxx>
- Date: Fri, 21 Sep 2001 15:55:30 -0400
Hello All,
I am looking for opinions on termination schemes for a QDR SRAM bus using
HSTL technology. In particular, a couple questions arise:
1) Just what does the ZQ impedance control do? Is this equivalent to a
source series resistor, when added to the driver impedance, matches the
target trace impedance? Or is it related to slew and/or current limits for
the driver?
2) Pros and cons of the different termination schemes (unterminated, source
series, parallel term at receiver, parallel term at receiver and driver,
others...).
3) For a bus with multiple devices (ie: FPGA + 4xSRAMs), is parallel term at
both ends of daisy-chain bus the only scheme useable for high speed
(150-200MHz) bus?
All opinions welcomed and appreciated.
thnx,
AAron
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