[SI-LIST] Re: HSPICE for 10Gbps link simulation?
- From: "McKinney, Steven" <Steven_McKinney@xxxxxxxxxx>
- To: "buenos@xxxxxxxxxxx" <buenos@xxxxxxxxxxx>, "si-list@xxxxxxxxxxxxx" <si-list@xxxxxxxxxxxxx>
- Date: Wed, 10 Oct 2012 01:22:04 +0000
Hi Istvan,
HyperLynx does offer integration to HSPICE. It's the same scenario, you need
to have HSPICE installed but it doesn't have to be local. You just need to
have the environment variable for the HSPICE install set and HyperLynx will
automatically pick it up and send the netlist to that location.
-Steve
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On
Behalf Of Istvan Nagy
Sent: Tuesday, October 09, 2012 8:10 PM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: HSPICE for 10Gbps link simulation?
Hi,
Thanks for the detailed explanations.
I have done some IBIS-AMI simulations a year ago on an ADS-trial version, but I
never had to deal with HSPICE so I didnt know anything about it.
I just found out few things:
-The HSPICE model we have has FFE/DFE in it, based on the pdf that came with
the model -Our vendor now provides IBIS-AMI models for the chip (which should
be supported by both ADS and Hyperlynx, We currently have Hyperlynx) -Agilent
ADS could simulate HSPICE models in certain cases, i think it also needs HSPICE
to be installed on the same PC. I didnt see any sign of this support in
Hyperlynx.
Todd, did you check out my LinkedIn profile today? -someone from your company
did.
Regards,
Istvan Nagy
Fortinet
-----Original Message-----
From: Todd Westerhoff
Sent: Tuesday, October 09, 2012 11:06 AM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: HSPICE for 10Gbps link simulation?
Arpad,
It's possible to run channel simulations with an IBIS-AMI model on one end of a
link and an encrypted HSPICE model on the other end - we do it all
the time. Note that this requires a HSPICE license and the analysis
assumes the HSPICE model's behavior does not vary on a bit by bit basis.
While we'd prefer to see IBIS-AMI models at both ends of the link, running a
mixed HSPICE/IBIS-AMI analysis is preferable to not being able to run
simulations at all.
Todd.
Todd Westerhoff
VP, Software Products
Signal Integrity Software Inc. â www.sisoft.com
6 Clock Tower Place â Suite 250 â Maynard, MA 01754
(978) 461-0449 x24 â twesterh@xxxxxxxxxx
âI want to live like that â
-Sidewalk Prophets
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
On Behalf Of Muranyi, Arpad
Sent: Monday, October 08, 2012 7:23 PM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: HSPICE for 10Gbps link simulation?
Istvan,
In order to answer your questions I would like to explain the nature of these
three different model types first.
HSPICE models are transistor level models, meaning that the buffer's circuit is
described by individual transistor models.
This means that what you have in the model pretty much corresponds to what the
buffer's designer works with in his schematic editor/simulator. You get a lot
of detail in these models, but it comes at the expense of slow simulations.
The detail, however, doesn't always mean better accuracy (as some tend to
believe). If the transistor's models are bad the buffer model will be just as
bad too. I have seen plenty of this before...
IBIS models are behavioral buffer models which are based on I-V curves and
Ramps or V-t curves. There is no circuit detail in these buffer models.
You characterize the buffer's impedance with the I-V curves, and their
switching characteristics with the Ramps or V-t curves. This is based on some
assumptions, and therefore is limited to certain types of circuits.
This simplification makes simulations much faster.
Both of the above model types, however, are used in circuit simulators which
solve the various circuit laws (Ohm's, Kirchoff's etc... laws). In the
presence of non-linearities, these simulators solve the circuits iteratively,
which is fairly time consuming.
However, the need for being able to simulate millions of bits worth of
waveforms required even faster simulations. This is why simulations based on
statistical and signal processing algorithms were invented.
IBIS-AMI models contain such signal processing algorithms. The input to these
models is an impulse response of the channel and the AMI models apply their
signal processing algorithms to that to obtain the results.
This can be done with statistical algorithms, or with time domain algorithms,
but no matter how you look at it, the algorithms do not solve for currents and
voltages, they process signals.
While you can theoretically get the same results from the transistor level
HSPICE models as the signal processing IBIS-AMI models, the question is how
long it takes to do that. If you include all the logic needed to model an
equalizer or CDR or DFE in a transistor model, you will have thousands of
transistors in that model which take an extremely long time to simulate. Add
to this that simulations to obtain very low probabilities of errors (BER) need
millions of bits to be simulated, you will quickly realize that this is simply
impossible to do in a reasonable amount of time.
I hope you are starting to get the wind by now, and see why you can't mix the
traditional circuit solving approaches with the signal processing approaches.
These two types of models are just fundamentally different and are used in
completely different ways in the simulation engines.
There are ways to combine the waveforms of these two types of simulations and
get "mixed mode" results, but it really doesn't make much sense to do it.
IBIS-AMI simulations are geared towards millions of bits worth of simulations.
Let's say you have a full transistor model for the Tx and and AMI model for the
Rx, in order to get just 1 million bits simulated in the Rx, you would have to
generate 1 million bits of waveforms with the Tx.
Try doing that with an HSPICE transistor level model. It will take you weeks
or longer just for one simulation, especially if the transistor model includes
all the taps and associated logic to model the EQ in the Tx. If you compromise
and run only a few hundred bits with the transistor level Tx model, then you
may not get a long enough waveform to even just get the Rx AMI model to "warm
up", i.e. to get its tap coefficients to settle, or the CDR to lock, etc...
I hope you can see from this why transistor level models, or even normal IBIS
models can't be mixed with AMI models.
Now, don't confuse this with the fact that for all AMI simulations you must
have a normal analog (IBIS) model to be able to run the channel
characterization simulation. In order to generate an impulse response for the
channel, you must connect the analog models of the buffers to the ends of the
channel to account for the impedance mismatches between the channel and buffer.
But this channel characterization is usually a fairly short simulation. Once
this is done, the rest is done with the AMI signal processing models, to find
the best tap coefficients, or other settings which are independent from the
channel's characteristics, such as stackup, trace dimensions, etc...
I hope this give you a better understanding of the nature of IBIS-AMI
simulations and the different model types.
Thanks,
Arpad
==========================================================================
==
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
On Behalf Of Istvan Nagy
Sent: Friday, October 05, 2012 9:48 PM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] HSPICE for 10Gbps link simulation?
Hi,
I have never used HSPICE only IBIS (and IBIS-AMI) based SI simulators.
Now it came up that we should simulate our 10Gbps/diffpair backplane-based
system in HSPICE, since we got HSPICE models but not IBIS-AMI for one of the
main chips.
I wanted to use Hyperlynx or Agilent ADS to put the system model together with
boards backplane and silicon models.
Does the HSPICE simulation deliver the same information as an IBIS-AMI based
channel simulation?
Does it also do fast statistical simulation or only bit-by-bit?
Can we include FFE and DFE-EQ in the simulation?
Best regards,
Istvan Nagy
Sr HWD Engineer
Fortinet, Sunnyvale
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