[SI-LIST] Re: HSPICE for 10Gbps link simulation?
- From: "Todd Westerhoff" <twesterh@xxxxxxxxxx>
- To: <si-list@xxxxxxxxxxxxx>
- Date: Thu, 11 Oct 2012 09:27:17 -0400 (EDT)
Chris (& all),
... that should have been "the proof is *in* the pudding. That's what I get
for responding from my phone while walking out the door this morning.
As I realize I'm making some pretty big claims and need to back them up, let
me point to the material we've presented at DesignCon over the past few
years. Some papers relevant to this discussion are:
- Simulating Large Systems with Thousands of Serial Links, DesignCon 2012
- Studying Clock Recovery Performance Using IBIS-AMI Models - DesignCon 2011
- Using IBIS-AMI Models to Study Clock Recovery Loop Performance - 2010
- Predicting BER with IBIS-AMI models (co-authored with IBM)- DesignCon 2010
- Demonstration of SerDes Modeling using the Algorithmic Model Interface
(AMI) Standard - DesignCon 2008
These and other papers are available on SiSoft's eLearning site; you can see
the list at http://www.sisoft.com/elearning/papers-and-presentations.html.
Note: SiSoft eLearning is a registered access site - you will need a login
to access the material.
Todd.
Todd Westerhoff
VP, Software Products
Signal Integrity Software Inc. â www.sisoft.com
6 Clock Tower Place â Suite 250 â Maynard, MA 01754
(978) 461-0449 x24 â twesterh@xxxxxxxxxx
âI want to live like that â
-Sidewalk Prophets
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On
Behalf Of Todd Westerhoff
Sent: Thursday, October 11, 2012 6:33 AM
To: chris.cheng@xxxxxx
Cc: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: HSPICE for 10Gbps link simulation?
Chris,
Again, you're entirely correct, the quality of the code really does matter.
Simulation always has been (and always will be) critically dependent on
model quality.
For what it's worth, all of the things you mentioned have been coded into
AMI models, many times. As always, the proof is on the pudding - how well
the model correlates to measurement.
Todd
--
Todd Westerhoff
VP, Software Products
SiSoft
6 Clock Tower Place, Suite 250
Maynard, MA 01754
(978) 461-0449 x24
twesterh@xxxxxxxxxx
www.sisoft.com
âI want to live like that"
-Sidewalk Prophets
On Oct 11, 2012, at 2:28 AM, "Cheng, Chris" <chris.cheng@xxxxxx> wrote:
> The way I see AMI algo is, a lot of times the application side had a hard
> time understanding the underlying circuits and abstract it in a way that
> is totally different from what the real equalizer does. E.g. using a zero
> forcing method from a pulse response and apply a fixed code for a DFE
> equalizer. I have yet to see an example how a bang bang CDR or a phase
> interpreter can be code up in AMI. How about when the CDR is actually tied
> into the DFE taps ? Or the Tx FIR has feedback from Rx DFE ?
> Itâs like giving you C language and then expect you to program the meaning
> of life. In theory, it's doable. In practice, not so sure.
> Chris Cheng
> Distinguished Technologist , Electrical Hewlett-Packard Company
>
> +1 510 413 5977 / Tel
> chris.cheng@xxxxxx / Email
> 4209 Technology Dr
> Fremont, CA 94538
> USA
>
>
>
>
> -----Original Message-----
> From: si-list-bounce@xxxxxxxxxxxxx
> [mailto:si-list-bounce@xxxxxxxxxxxxx] On Behalf Of Todd Westerhoff
> Sent: Wednesday, October 10, 2012 12:43 PM
> To: si-list@xxxxxxxxxxxxx
> Subject: [SI-LIST] Re: HSPICE for 10Gbps link simulation?
>
> Chris,
>
> You're entirely correct - which is why a full-on AMI model for the RX
> is preferable. You have the ability to simulate millions of bits,
> model the adaptive behavior of the equalizer and the interactions with
> the clock recovery circuit.
>
> My original response was based on "if all I have is an HSPICE model,
> then ...". In that case, I maintain an LTI approximation is better
> than no analysis at all.
>
> Engineering judgment applies, of course. The user has to be able to
> understand the bounds of the result and how to apply it in practice.
>
> Todd.
>
> Todd Westerhoff
> VP, Software Products
>
> Signal Integrity Software Inc. â www.sisoft.com
> 6 Clock Tower Place â Suite 250 â Maynard, MA 01754
> (978) 461-0449 x24 â twesterh@xxxxxxxxxx
>
>
> âI want to live like that â
> -Sidewalk Prophets
>
>
>
> -----Original Message-----
> From: si-list-bounce@xxxxxxxxxxxxx
> [mailto:si-list-bounce@xxxxxxxxxxxxx] On Behalf Of Cheng, Chris
> Sent: Wednesday, October 10, 2012 2:42 PM
> To: si-list@xxxxxxxxxxxxx
> Subject: [SI-LIST] Re: HSPICE for 10Gbps link simulation?
>
> Having a FFE and DFE in HSPICE is only a small part of your analysis.
> The output of the DFE is the slicer decisions which are ones and
> zeros, it doesn't tell you anything about your channel margin nor it
> gives you any eye diagram.
> Your DFE slicer samples its input based on a lot of possible clocking
> way including but not limited to CDR, phase interpreter or PLL. Have
> you ever try to make a PLL dynamically locked to the reference phase in
> HSPICE ?
> Let's just say you decided to use algo based AMI to simulated
> "millions of cycles" as suggested below, how does the LTI work when
> the DFE is a dynamic changing equalizer that alter the input according to
> previous output.
> Let's just say you stick with full circuit cycle to cycle simulations.
> That means you have to use some form of peak distortion to converge to
> worst case patterns. How does that work when the DFE feedback alter
> the input according to different post cursor patterns. How do you
> figure out what is the worst case pattern then ?
> I am just saying......
> Chris Cheng
> Distinguished Technologist , Electrical Hewlett-Packard Company
>
> +1 510 413 5977 / Tel
> chris.cheng@xxxxxx / Email
> 4209 Technology Dr
> Fremont, CA 94538
> USA
>
>
>
>
> -----Original Message-----
> From: si-list-bounce@xxxxxxxxxxxxx
> [mailto:si-list-bounce@xxxxxxxxxxxxx] On Behalf Of Todd Westerhoff
> Sent: Wednesday, October 10, 2012 5:54 AM
> To: si-list@xxxxxxxxxxxxx
> Subject: [SI-LIST] Re: HSPICE for 10Gbps link simulation?
>
> Arpad,
>
> In the scenario I described, the simulation time is longer, but not
> significantly so.
>
> For what it's worth, I'm doubtful that the vendor has been provided a
> transistor-level model that models DFE equalization and adaptation in
> a significant way. If so, it will be the first one I've seen.
>
> Todd.
>
> Todd Westerhoff
> VP, Software Products
>
> Signal Integrity Software Inc. â www.sisoft.com
> 6 Clock Tower Place â Suite 250 â Maynard, MA 01754
> (978) 461-0449 x24 â twesterh@xxxxxxxxxx
>
>
> âI want to live like that â
> -Sidewalk Prophets
>
>
> -----Original Message-----
> From: si-list-bounce@xxxxxxxxxxxxx
> [mailto:si-list-bounce@xxxxxxxxxxxxx] On Behalf Of Muranyi, Arpad
> Sent: Tuesday, October 09, 2012 11:50 PM
> To: si-list@xxxxxxxxxxxxx
> Subject: [SI-LIST] Re: HSPICE for 10Gbps link simulation?
>
> Istvan,
> We can take the HyperLynx specific details off line, but for now, as
> you saw it from Steve's reply, we do have the capability to run HSPICE
> as the simulation engine from HyperLynx. If your vendor is willing to
> let you have the unencrypted models, we could most likely even run
> them with our own SPICE engine called Eldo for which you would not
> need to have the HSPICE license. Or, if they are not willing to give
> you the unencrypted model files we can send them an encryption utility
> and have them do the encryption for Eldo and let them send you the
> Eldo encrypted files. We can work out the details off line (even in
> Hungarian if you like)...
>
>
> So is this HSPICE model for the Tx or the Rx? Considering that you
> mentioned that it has FFE/DFE in it, I would think it is for the Rx.
>
> Are you thinking of using an IBIS-AMI Tx model and use this HSPICE Rx
> model on the other end of the channel? Did you run any simulations
> with this HSPICE model to have an idea for how much time it needs for the
> simulations?
> I wonder how long it would take to run a 1 million bit simulation and
> how many ignore bits you need to throw away before you see a reasonable
> eye.
>
> Regarding Todd's comments in this thread, while I agree that it is
> possible to use an IBIS-AMI Tx model with the transistor Rx model, I
> wonder whether the simulation time is prohibitively large. The
> linearization Todd mentioned would not help to speed up the time it
> takes to push the waveforms through the transistor level FFE/DFE
> logic, unless you find a way to "convert" those to some sort of
> "behavioral" or "algorithmic" equivalents and simulate them that way.
> But these types of conversions are not necessarily easy or accurate,
> unless you are very familiar with what is inside the transistor model and
> know what you are after.
>
> Remelem, hogy beszelhetunk errol tobbet talan meg magyarul is...
>
> Arpad
> ==================================================================
>
>
>
>
>
> -----Original Message-----
> From: si-list-bounce@xxxxxxxxxxxxx
> [mailto:si-list-bounce@xxxxxxxxxxxxx] On Behalf Of Istvan Nagy
> Sent: Tuesday, October 09, 2012 8:10 PM
> To: si-list@xxxxxxxxxxxxx
> Subject: [SI-LIST] Re: HSPICE for 10Gbps link simulation?
>
> Hi,
>
> Thanks for the detailed explanations.
> I have done some IBIS-AMI simulations a year ago on an ADS-trial
> version, but I never had to deal with HSPICE so I didnt know anything
> about it.
>
> I just found out few things:
> -The HSPICE model we have has FFE/DFE in it, based on the pdf that
> came with the model -Our vendor now provides IBIS-AMI models for the
> chip (which should be supported by both ADS and Hyperlynx, We
> currently have
> Hyperlynx) -Agilent ADS could simulate HSPICE models in certain cases,
> i think it also needs HSPICE to be installed on the same PC. I didnt
> see any sign of this support in Hyperlynx.
>
> Todd, did you check out my LinkedIn profile today? -someone from your
> company did.
>
> Regards,
> Istvan Nagy
> Fortinet
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