[SI-LIST] Re: HSPICE for 10Gbps link simulation?
- From: "Muranyi, Arpad" <Arpad_Muranyi@xxxxxxxxxx>
- To: "twesterh@xxxxxxxxxx" <twesterh@xxxxxxxxxx>, "si-list@xxxxxxxxxxxxx" <si-list@xxxxxxxxxxxxx>
- Date: Wed, 10 Oct 2012 16:18:23 +0000
Todd,
Sorry to be so slow in understanding you, but I am still
confused. How can you say that "We run channel simulations
with HSPICE models on either one or both sides of the link."
when you also say "...although I've never seen such a model."?
This discussion started with the question on whether one can
mix AMI and SPICE models in channel analysis, which I assumed
was asked in the context of generating eye diagrams and BER
plots for millions of bits (not just a few tens or hundreds
of bits). How can you do that with a SPICE Rx model that
doesn't include DFE and/or any other EQ blocks?
If this assumption on my part was incorrect, and we are talking
about simulations using conventional buffers which don't have
EQ-s, CDR-s, DFE-s, etc... we can all say that we are doing
it all the time... But who would make an IBIS-AMI model for
that purpose?
Thanks,
Arpad
================================================================
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On
Behalf Of Todd Westerhoff
Sent: Wednesday, October 10, 2012 10:26 AM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: HSPICE for 10Gbps link simulation?
Arpad,
We run channel simulations with HSPICE models on either one or both sides of
the link.
As I said, we make the assumption that the HSPICE model's behavior does not
change on a bit by bit basis. DFE adaptation in a HSPICE transistor model
would invalidate that assumption, although I've never seen such a model.
Todd.
Todd Westerhoff
VP, Software Products
Signal Integrity Software Inc. â www.sisoft.com
6 Clock Tower Place â Suite 250 â Maynard, MA 01754
(978) 461-0449 x24 â twesterh@xxxxxxxxxx
âI want to live like that â
-Sidewalk Prophets
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On
Behalf Of Muranyi, Arpad
Sent: Wednesday, October 10, 2012 10:46 AM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: HSPICE for 10Gbps link simulation?
Todd,
I was wondering about that myself...
But to double check, were you referring only to a SPICE Tx and AMI Rx
configuration in your first reply to this thread?
"It's possible to run channel simulations with an IBIS-AMI model on one end
of a link and an encrypted HSPICE model on the other end - we do it all the
time."
Given your statement "I'm doubtful that the vendor has been provided a
transistor-level model that models DFE equalization and adaptation in a
significant way.", I don't see how you could do the reverse, i.e. AMI Tx and
SPICE Rx modeling, or if the SPICE Rx model includes the whole thing I doubt
anyone would have the time to wait for the results to arrive...
So what is it that you do "all the time"?
Thanks,
Arpad
=====================================================================
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On
Behalf Of Todd Westerhoff
Sent: Wednesday, October 10, 2012 7:54 AM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: HSPICE for 10Gbps link simulation?
Arpad,
In the scenario I described, the simulation time is longer, but not
significantly so.
For what it's worth, I'm doubtful that the vendor has been provided a
transistor-level model that models DFE equalization and adaptation in a
significant way. If so, it will be the first one I've seen.
Todd.
Todd Westerhoff
VP, Software Products
Signal Integrity Software Inc. â www.sisoft.com
6 Clock Tower Place â Suite 250 â Maynard, MA 01754
(978) 461-0449 x24 â twesterh@xxxxxxxxxx
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