[SI-LIST] Re: HSPICE Vs. IBIS models

  • From: "Ingraham, Andrew" <a.ingraham@xxxxxxxx>
  • To: "Si-List" <si-list@xxxxxxxxxxxxx>
  • Date: Thu, 22 Jan 2004 13:49:54 -0500

> Generally - the signal are alike, the only issue is that the when I
> simulate with the IBIS model the timing is lagging by about 200ps in the
> Slow corner and 50ps in the Fast corner.

Do you mean that the waveforms compare well, but that they are shifted in

IBIS models model just the output portion of the output buffer, just the
part of the circuit that interacts with the external circuit connections.

SPICE models can represent the output transistors, or the whole output
buffer, or the whole IC if you want.  Each case would give the SPICE
simulation a different delay from input-to-output of the SPICE model.

You could even have a SPICE model of an output buffer that has a 500ns
delay-line in it; but when you convert it to IBIS (without rising/falling
waveforms), that delay information is gone.  IBIS just gives you a
simulation of what the output waveform looks like, with no absolute timing
reference.  (HSPICE's implementation of IBIS does give you a "buffer" which
seems to have a stimulus input "pin" and a delay, but it's artificial.)

Even if the IBIS model had rising/falling waveform tables, simulators don't
need to use them.


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