[SI-LIST] Re: HSPICE Field Solver
- From: "ruston, matt" <ruston_matt@xxxxxxx>
- To: "'mido@xxxxxxxxxxxxxx'" <mido@xxxxxxxxxxxxxx>,marekski@xxxxxxxxxxxxxxxxxx
- Date: Tue, 16 Oct 2001 13:53:17 -0400
Assuming his maintenance is paid up!!! :^)
-----Original Message-----
From: Ted Mido [mailto:mido@xxxxxxxxxxxxxx]
Sent: Tuesday, October 16, 2001 1:44 PM
To: marekski@xxxxxxxxxxxxxxxxxx
Cc: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: HSPICE Field Solver
Hi Marek:
I think your signal conductors are overlapped on the upper reference
plane...(Is it what you want?)
Please send this type of problem to Avant! technical support
from next time you find problem(s) with Hspice.
ted mido @ avant!
From: "Marek Skibinski" <marekski@xxxxxxxxxxxxxxxxxx>
Subject: [SI-LIST] HSPICE Field Solver
Date: Tue, 16 Oct 2001 15:54:00 +0100
> Guys,
>
> I am running HSPICE 2001.2 to do SI work on a Backplane. Unfortunately the
> field solver within HSPICE is giving me suspect results. Here is the code
> that I am using for my W element setup:
>
> ___________________________________________________
> * Track shape definiton widths to suit
>
> .SHAPE rect RECTANGLE WIDTH=0.0001016m, HEIGHT=0.00001778m,
>
> * Preliminary layer stack
>
> .LAYERSTACK stack_1,
> +LAYER=(PEC,0.00001778m), LAYER=(getek,0.000381m),
> +LAYER=(PEC,0.00001778m)
>
> * Setting field solver options to high accuracy
>
> .FSOPTIONS opt1_1 GRIDFACTOR=3 PRINTDATA=YES
> +ComputeRo=yes ComputeRs=yes ComputeGo=yes ComputeGd=yes
>
> *-----------------------------------------------------------------------
> * Tx Card T-line
> *
>
> .MODEL tx_card_line W MODELTYPE=FieldSolver,
> +LAYERSTACK=stack_1, FSOPTIONS=opt1_1
> +RLGCFILE=txcardli.rlgc
> +CONDUCTOR=(MATERIAL=copper, SHAPE=rect, ORIGIN=(0m,0.00038989m)),
> +CONDUCTOR=(MATERIAL=copper, SHAPE=rect, ORIGIN=(0.0002289m,0.00038989m))
>
> ________________________________________________________
>
>
> And here is the resulting rlgc file:
>
> _________________________________________________________
> *SYSTEM_NAME : tx_card_line
> *
> * ------------------------------------ Z = 4.1656e-07
> * //// Top Ground Plane //////////////
> * ------------------------------------ Z = 3.9878e-07
> * getek H = 3.81e-07
> * ------------------------------------ Z = 1.778e-08
> * //// Bottom Ground Plane ///////////
> * ------------------------------------ Z = 0
>
> * L(H/m), C(F/m), Ro(Ohm/m), Go(S/m), Rs(Ohm/(m*sqrt(Hz)), Gd(S/(m*Hz))
>
> .MODEL tx_card_line W MODELTYPE=RLGC, N=2
> + Lo = 2.82310e-08
> + 0.00000e+00 2.82310e-08
> + Co = 1.53499e-09
> + 0.00000e+00 1.53499e-09
> + Ro = 9.61063e+06
> + 0.00000e+00 9.61063e+06
> + Go = 0.00000e+00
> + 0.00000e+00 0.00000e+00
> + Rs = 1.05871e+00
> + -2.46652e-03 1.05871e+00
> + Gd = 9.64460e-11
> + 0.00000e+00 9.64460e-11
>
> ______________________________________________________
>
>
> The results from the SigXplorer field solver indicate different values by
a
> factor of 10 in both capacitance and inductance of the track.
>
> Could you have a look at the code and tell me if there is a problem with
> the field solver or am i just missing something a bit more fundamental.
>
> Thanks for your help,
>
> Marek
>
> **********************************************************
> Marek Skibinski
> Hardware Design Engineer
> Nortel Networks
> Doagh Road, Newtownabbey, Co. Antrim
> BT36 6XA
> Tel: +44 (0)2890363494 (ESN 751-3494)
> **********************************************************
>
>
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